A New Device Model of Amorphous Silicon Thin-Film Transistor for Circuit Simulation
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A NEW DEVICE MODEL
OF AMORPHOUS SILICON THIN-FILM TRANSISTOR FOR CIRCUIT SIMULATION
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Hong S. Choi , Jin S. Park, Chang H. Ohs. In S. Joo, Yong S. Kim, Min K. Han, Yearn 55 I. Choi , Jung G. Yun', Won K. Parks, and Woo Y. Kim* Seoul Nat'l. Univ., Dept. of Electrical Eng., Kwanak-Ku, Seoul 151-742, Korea *GoldStar Co., LTD., R & D Complex, An-Yang 430-080, Korea *SAjou Univ., Dept. of Electronics Eng., Suwon 440-749, Korea
ABSTRACT We present a new analytical model of amorphous silicon thin-film transistor (a-Si TFT) suitable for circuit simulators such as SPICE. The effects of localized gap state distributions of a-Si as well as temperatures on the a-Si TFT performances have been fully considered in the presented model. The parameters used in SPICE, such as transconductance, channel-length modulation, and power factor of source-drain current, are evaluated from the measured current-voltage and capacitance-voltage characteristics by employing the proposed extraction method. It has *been found out that the analytical model is in good agreement with experimental dat~a at both room temperature and elevated temperature and successfully implemented in a widely used circuit simulator. INTRODUCTION Amorphous silicon (a-Si) thin-film transistors (TFT's) have been utilized for large area electronic applications such as flat-panel liquid-crystal displays, solid-state image sensors, and high-resolution displays [1-3]. As a-Si TFT integrated circuits are getting more complex, an accurate circuit simulation is desired. However, the widely used circuit simulator, such as SPICE 14], lacks a suitable model for a-Si TFT. Due to the localized gap state distributions of a-Si and the inverted-staggered TFT configurations, the conventional crystalline silicon (c-Si) MOSFET model incorporated into the SPICE may not be adopted to characterize the a-Si TFT integrated circuits. The purpose of our work is to present a new analytical model suitable for circuit simulation. The localized gap states of a-Si and various operating temperature effects on the a-Si TFT device performances have been characterized experimentally and fully implemented in the presented model. The current-voltage and capacitance-voltage characteristics of a-Si TFT are analytically expressed according to various operating regimes such as below threshold, linear, and saturation regimes. The parameters used in our analytical model for SPICE have been succesfully extracted at different operating regimes from the experimental data. ANALYTICAL MODELING OF a-Si TFT An analytical model describing current-voltage and capacitance-voltage characteristics of an a-Si TFT has been presented. Our model is based on the carrier transport mechanisms considering continuous distributions of localized states within the mobility gap of amorphous silicon. A schematic diagram of an inverted staggered a-Si TFT with element of small-signal equivalent circuit and a potential profile along the gate insulatorla-Si direction are shown in figure 1. The operation of a-Si TFT is quite different from
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