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Amorphous Silicon Vertical Thin Film Transistor for High Density Integration Isaac Chan and Arokia Nathan Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, N2L 3G1, Canada ABSTRACT This paper presents a fabrication process for vertical thin film transistors (VTFT) based on hydrogenated amorphous silicon (a-Si:H) technology. This process yields VTFTs with an ON/OFF ratio of 105 and a leakage current of the order of 10-13A for a channel length of 1 µm. The device structure, because of significant undercutting formed after dry-etch process (reactive ion etching or RIE), has a channel profile that is skewed as opposed to vertical. This serves to compromise the structural integrity and the electrical performance of the device. Therefore, an anisotropic dry-etch process for this channel profile is being developed. It is found that a CF4/20%H2 gas mixture yields a sharp vertical sidewall profile. In addition, a modified masking process has been developed to produce a rectangular photoresist profile so as to achieve an anisotropic etch profile for the channel region. The effects of the photoresist geometry on the anisotropic dry-etch process will be discussed. INTRODUCTION The vertical thin film transistor in amorphous silicon (a-Si:H) technology appears to be a highly attractive structural alternative to improve the switching performance of the TFT (Figure 1). The VTFT lends itself naturally to scaling down of the channel length into sub-micron dimensions (defined by the dielectric film thickness) without being limited by photolithographic resolution, as in the case for conventional (lateral) TFTs. From a geometrical standpoint, arranging the various layers and active components in a vertical orientation also offers considerable savings in device area, compared to that achievable using conventional TFT structures. In applications where high device/pixel packing density is required, VTFTs have a distinct advantage in terms of the pixel size and fill factor. All these merits warrant the development of a small-area VTFT process suitable for high-density large-area electronics.

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Vertical TFT Conventional TFT Figure 1. Schematics of the conventional and vertical TFT structures (not to scale).

A12.6.1 Downloaded from https://www.cambridge.org/core. The Librarian-Seeley Historical Library, on 04 Feb 2020 at 08:11:15, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/terms. https://doi.org/10.1557/PROC-715-A12.6

EXPERIMENTAL DETAILS A five-mask VTFT process was developed (see Figure 2 and Table I) based on the structure proposed by Uchida et al. [1]. It starts with source, drain, and gate patterning sequentially in three masks. For the source, Mo is sputter deposited, followed by plasma-enhanced chemical vapour deposition (PECVD) of n+ a-Si:H / a-SiNx:H bi-layer in one pump-down process. The bilayer is patterned by SF6/O2 dry-