A novel architecture design for VLSI implementation of integer DCT in HEVC standard
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A novel architecture design for VLSI implementation of integer DCT in HEVC standard Hassen Loukil 1,2
& Nouri Masmoudi
2
Received: 19 September 2019 / Revised: 30 May 2020 / Accepted: 4 June 2020 # Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract
This paper presents novel hardware of a unified architecture to compute the 4 × 4, 8 × 8, 16 × 16 and 32 × 32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications. Keywords HEVC . ICT . FPGA . VHDL . Embedded video system
1 Introduction Many commercial products in consumer electronic devices use Video compression systems which demands aggressive video compression requirement such as UHD 4 K/8 K TV [14], unmanned aerial vehicle (UAV) reconnaissance and surveillance [2, 3].
* Hassen Loukil [email protected]
1
Electrical Engineering Department, College of Engineering, King Khalid University, Abha, Asir 61413, Saudi Arabia
2
National School of Engineering, Electronics and Information Technology Laboratory, University of Sfax, 3038 Sfax, Tunisia
Multimedia Tools and Applications
Recently, the joint collaborative team on video coding developed the new video coding standard High Efficiency Video Coding (HEVC) which provides more coding efficiency. This standard uses the same hybrid block-based motion estimation and transforms coding as the previous video coding standard. The process of encoding to produce an HEVC compliant bitstream would proceed as Fig. 1 show. Each picture is divided into sub-block using the quadtree structure. The first picture of the video sequence is usually intra coded. For the other pictures, both intra prediction and inter prediction can be used. The residual Block which is the difference between the original block and the prediction block is transformed, scaled then quantized. Finally, the entropy coding is realized, in order to be transmitted with the prediction information to the decoder [9]. For HEVC, the two-dimensional transform is computed by applying the one-dimensional transform in both horizontal and vertical
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