The VLSI Architecture and Implementation of a Low Complexity and Highly Efficient Configurable SVD Processor for MIMO Co
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The VLSI Architecture and Implementation of a Low Complexity and Highly Efficient Configurable SVD Processor for MIMO Communication Systems Wei-Jhe Chen1 · Yu-An Lai1 · Chung-An Shen1 Received: 6 August 2019 / Revised: 15 May 2020 / Accepted: 16 May 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper presents the design and implementation of a low complexity and highly efficient configurable singular value decomposition (SVD) processor for 2 × 2, 4 × 4, 6 × 6, and 8 × 8 MIMO wireless communication systems. In order to minimize the area complexity while maintaining comparable throughput, novel data-processing sequences are proposed so that costly matrix multipliers are eliminated. Furthermore, data dependencies are greatly mitigated due to the proposed processing sequences. Therefore, a highly optimized pipelined architecture is designed where the resource utilization and hardware efficiency are significantly improved. Moreover, circuit level optimizations are also applied to further enhance the performance of the proposed SVD processor. The proposed SVD architecture has been implemented with 90 nm technology at 500 MHz clock frequency. The post-layout estimations show that the proposed SVD processor achieves a throughput of 1.1 M matrices/s for 8 × 8 MIMO communication systems with the hardware complexity of 192.2 kilo Gate Equivalents. Compared to the state-of-the-art design that supports 2 × 2, 4 × 4, 6 × 6, and 8 × 8 MIMO configurations, the proposed architecture demonstrates a 46% reduction in area complexity and a 22% improvement in hardware efficiency. Keywords MIMO · Singular value decomposition (SVD) · Configurability · VLSI · Circuit · Hardware-efficient
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Chung-An Shen [email protected] Wei-Jhe Chen [email protected] Yu-An Lai [email protected]
1
Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan, ROC
Circuits, Systems, and Signal Processing
1 Introduction Multiple-input and Multiple-output (MIMO) technology [12, 15] is widely used in modern wireless communication systems for enhancing data rate and improving signal quality [1, 4]. It has also been shown [5, 18] that precoding the transmitted signal at the transmitter side enhances the signal quality and reduces the complexity at the receiving end of the MIMO system. Specifically, the linear precoding scheme based on singular value decomposition (SVD) has been widely adopted in MIMO communications owing to its friendly structure for VLSI designs [2, 5, 6, 8, 9, 18–20]. In principle, the SVD-based precoding decomposes the channel matrix into a series of multiplications between complex-value unitary matrices and a real-valued diagonal matrix that contains singular values. This real-valued diagonal matrix decomposes the MIMO communication channel to become independent parallel sub-channels and the signal interferences among antennas are eliminated due to the characteristic of the diagonal matrix. Thus, a much simpl
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