A Novel Low Power Architecture for DLL-Based Frequency Synthesizers
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A Novel Low Power Architecture for DLL-Based Frequency Synthesizers Mohammad Gholami
Received: 18 November 2011 / Revised: 29 August 2012 / Published online: 19 September 2012 © Springer Science+Business Media, LLC 2012
Abstract This paper presents a novel DLL-based frequency synthesizer architecture to generate fractional multiples of reference frequency and reduce the power consumption of the frequency synthesis block. The architecture is adopted for French VHF application as an example. The DLL architecture allows for minimal area, while consuming low power. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. It was shown that for the mentioned standard, a mere 27 delay stages for VCDL are sufficient to cover French VHF band. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is implemented in a 0.13 µm CMOS technology. This fractional DLL-based frequency synthesizer is adopted for 176 MHz to 216 MHz with maximum power consumption of 2.62 mW and RMS jitter of 10 ps @ 216 MHz. Keywords Delay Locked Loop · Fractional multiple · Frequency synthesizer · Jitter · Phase noise
1 Introduction Frequency synthesizers are fundamental building blocks in the implementation of numerous communication systems. Nowadays PLL-based frequency synthesis is widely employed in wireless systems. Another approach that draws attention is Delay Locked Loop (DLL) -based frequency synthesis. DLLs find wide application in areas
M. Gholami is now part of Micro-Electronic Research Group in Babol University of Technology, Babol, Mazandaran, Iran. M. Gholami () Electrical Engineering Department, Sharif University of Technology, Tehran, Iran e-mail: [email protected]
782 Table 1 Comparison of DLLs with PLLs
Circuits Syst Signal Process (2013) 32:781–801 PLLs
DLLs
VCO with jitter accumulation
VCDL without jitter accumulation
Higher order systems and can be unstable
First-order systems and inherently stable
Slow lock
Fast lock
Hard to integrate loop filter
Easy to integrate loop filter
Hard to design
Easier to design
More jitter
Lower jitter
Higher phase noise
Lower phase noise
Less reference signal dependent
Reference signal dependent
Can multiply reference frequency
Cannot multiply reference frequency without edge combiner
Fig. 1 The block diagram of a conventional DLL-based frequency synthesizer
such as communication, clock skew [5], clock recovery circuits [4], wireless systems, digital circuits and frequency multipliers [8, 9, 18]. Recently, frequency synthesizers gained increased interest mainly in wireless applications where fast carrier frequency lock is required [10, 15, 22]. When there is no need to multiply the reference frequency, DLLs are used because of their low jitter and good phase noise performance and stability [12, 16]. Because of being a first-order system they are naturally stable [13]. Moreover, they offer a fast-locking time, easier design and integrated loop filter [3]. T
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