A novel low power and highly efficient inverter design
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ORIGINAL RESEARCH
A novel low power and highly efficient inverter design Sapna Sharma1 • Robinson Devasia1 • Geetanjali Sharma1
Received: 12 July 2019 / Accepted: 26 August 2020 Ó Bharati Vidyapeeth’s Institute of Computer Applications and Management 2020
Abstract The field of VLSI is evergreen and always growing. Tremendous amount of work is done to embed more gates on a given chip area. This makes it difficult to remove the generated heat. This problem can be solved by using low power circuits. Adiabatic logic style which is advancement over CMOS in terms of power dissipation is a good solution suggested by researchers. In this paper an entirely new approach is presented to address this problem. The proposed circuit dissipates least power as compared to other power saving logic styles. A comparative analysis of all the three logic styles has been presented for better understanding. The circuits are implemented and simulated on Tanner V.13 using 90 nm technology. Keywords CMOS Adiabatic circuits Inverter ECRL RTL DTL TTL
1 Introduction We all are aware of devices like smart phones, laptops, smart watches, etc. These have become an integral part of our lives today. Each of them consumes power and hence power consumption has become a point of research for
& Geetanjali Sharma [email protected] Sapna Sharma [email protected] Robinson Devasia [email protected] 1
Electronics and Communication Engineering Department, GGSIPU University, New Delhi, India
many researchers. Since batteries supply limited power, the circuits must consume less power [1, 2]. There are many logic families that we study in digital circuits. They include TTL, DTL, CMOS, etc. [3, 4]. Each family has some advantage over other. CMOS is preferred where least power dissipation is required. Although the power dissipation in CMOS is low compared to other logic families, it still dissipates a considerable amount of power during switching events in the form of heat. Voltage scaling is one of the solutions suggested to decrease the power dissipation of circuits. It helps in reducing the active losses. On the other hand it increases the delay of the circuit which is a disadvantage of this approach [5]. The retractile cascades allow to recover energy from outputs providing a solution to the problem of power dissipation. It however compromises with the performance of the circuit and hence is not very feasible solution [5]. Another technique suggested by researcher is adiabatic logic. Adiabatic logic style works on the principle of recycle/reuse of energy [6, 7]. In this logic style a part of energy supplied by power clock/supply is returned to the power clock/supply during the recycle phase. Though the adiabatic logic style reduces the power loss to a great extent, but it has some limitations. Increase in transistor count is the major issue encountered in such logic styles. In [8] ECRL NOT gate has been discussed which increases the transistor count to almost double compared to conventional CMOS logic style. The proposed logic styl
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