A novel method for minimizing transient current test time by exploiting RES in SRAM
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A novel method for minimizing transient current test time by exploiting RES in SRAM Princy Prince1
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Sivamangai N. M. 1
Received: 6 May 2020 / Revised: 23 August 2020 / Accepted: 3 November 2020 Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract As technology advances, circuit density and complexity increases in integrated circuits which make the devices vulnerable to different types of manufacturing defects. In such cases, even the occurrence of a fault may be critical. Hence, ensuring Static random access memory (SRAM) reliability and quality with high priority is essential. In this paper, an innovative approach to SRAM testing—wavelet-based transient supply current testing with modified March sequence exploiting read equivalent stress (RES) is introduced for fault detection. The main contribution of this research work is the unique testing solution that ensures a minimum test time for the detection of open defects in SRAMs. In comparison with other techniques that solely rely on the hardware implementation for fault detection, the proposed technique reduces design parameters, such as the area overhead, power consumption, hardware complexity and performance overhead. The simulation results demonstrate that the proposed technique can provide high reliability and efficiency and reduce test time (25%) compared to other methods. A complete evaluation of the proposed technique in terms of the overall memory performance is presented in this work. The main objective of this study is to investigate the efficiency of wavelet-based transient current test in detecting all open defects targeted in this work in SRAMs amidst process variations. Moreover, the conventional test time of transient current test is minimized exploiting the effects of RES. Keywords SRAM Wavelet Testing Transient Open defects
1 Introduction As technology continues to scale, yield and test quality increasingly relies on Static random-access memory (SRAM) blocks which consume a substantial amount of the overall chip area. Due to aggressive scaling, complex manufacturing process and high packing density, SRAMs are prone to various types of subtle lithographic imperfections and reliability issues [1]. Moreover, process parameter induced device variations and imperfections due to complex manufacturing process result in a growing number of marginal and hard-to detect defects [2–4]. Fault primitive (FP) is a precise, compact mathematical & Princy Prince [email protected] Sivamangai N. M. [email protected] 1
Department of ECE, Karunya Institute of Technology and Sciences, Coimbatore, India
representation which explains the operation performed in the memory cell, the cell contents after the senzitation operation and the response of the sense amplifier. Using the concept of FP one can derive all types of faulty behavior and it establishes a framework for all faults in the memory cell. As per the mode of sensitization, faults can be classified as static and dynamic. Static faults are those FPs, which can be sensitized by
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