A Study of Quasi-Breakdown Mechanism in Ultrathin Gate Oxide Under Various Types of Stress
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In this work. systematic experiments were conducted to investigate degradation of ultra thin gate oxide under various kinds of stress. Evolution of interface trap was monitored in MOSFET and MOS capacitor until quasi-breakdown. The effect of both substrate hot hole and hot electron injections into the gate oxide on QB was studied as well, because in real device operation. hot carrier injection into the gate oxide is also an important limiting factor in device lifetime. The changes of interface trap densities under various kinds of carrier injections are also discussed. Finally. an appropriate QB model based on those observations is proposed. EXPERIMENTS: CMOSFETs and MOS capacitor structures with a gate oxide thickness range of 3.5 - 4.5 nm were fabricated using twin well and dual polysilicon gate CMOS technology. The evolution of the amount of interface trap density during high field constant current stress (CCS) was mornitored on p'-polysilicon gate p-MOSFET with W/L = 50 .tm / 0.5 pim by using DCIV technique [6]. Fig. 1 shows the schematic diagram of our test structure of DCIV technique [7]. High field CCS was implemented with a wide range of current density between 0. 1 to 300 mA/cm 2 for both polarities. The interface trap was measured by interrupting the CCS periodically. 105
Mat. Res. Soc. Symp. Proc. Vol. 592 © 2000 Materials Research Society
For substrate hot hole injection, a test structure shown in Fig. 2 was used. The MOSFETs with W/L = 1) pm /1 pm were used for this experiment. Substrate hot holes were injected using p-MOSFET at a fixed gate voltage (Vg) of -5.2 V and well voltage (Vwe,)of 7 V. The amount of substrate hot hole injection is controlled by a forward bias ( Vi.) applying to the p-n junction between p-substrate and n-well. Substrate hot electrons were injected using n-MOSFET on pwell. Vg was fixed at 4.5 V and the Vwe, at - 7 V, with grounding the source and drain. In this case, adjacen n-well was used for the forward biased p-n junction for controlling the amount of substrate hot electron injection. Semiconductor Parameter Analyser
V9
Emitter
Emitter
VEB
Base
VoC
Collector
n- well p.Sub
Fig. 1. Cross-sectional schematic view of DCIV setup. A vertical parasitic p/n/p-BJT is used with tie condition Of VEB = +0.3 V (forward biased) and V BC.= 0 V. The interface trap density can be calculated from the peak value of Albll.
Fig. 2. A schematic of cross section of test structure and bias conditions for substrate hot hole injection. The amount of substrate hot hole injection is controlled by a forward bia Vmj.
RESULTS AND DISCUSSIONS: OB under F-N Stress During the CCS, the ultra thin gate oxide showed typical three stage degradation modes, SILC, QB, and complete breakdown (CB) as reported in previous literatures [ 1-4]. The inset of Fig. 3 shows the DCIV spectra in p-MOSFET with 37 A gate oxide, measured after each stress time, under the CCS with a current density of -20 mA/cm2 . The time indicated in the figure denotes the accumulated stress time. The peak values of bulk current in
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