Reliability of Oxide Thin Film Transistors under the Gate Bias Stress with 400 nm Wavelength Light Illumination
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Reliability of Oxide Thin Film Transistors under the Gate Bias Stress with 400 nm Wavelength Light Illumination Soo-Yeon Lee1, Sun-Jae Kim1, Yongwook Lee1,2, Woo-Geun Lee2, Kap-Soo Yoon2, Jang-Yeon Kwon3, and Min-Koo Han1 1
School of Electrical Engineering and Computer Science, Seoul National University, Seoul, Republic of Korea 2 Samsung Electronics, Yongin-Si, Republic of Korea 3 Department of Materials Science and Engineering, Seoul National University, Seoul, Republic of Korea
ABSTRACT We have investigated the reliability of the inverted-staggered etch stopper structure oxidebased TFTs under negative gate bias stress combined with 400 nm wavelength light illumination and the relationship between the carrier concentration at the channel and the extent of Vth shift. It was found that the photo-induced holes cause the severe Vth degradation at the beginning of stress and the hole trapping rate of a single hole is not altered with the increase of the hole concentration. In oxide-based TFTs, the hole concentration at the channel is the determinant factor of the reliability. INTRODUCTION Recently, amorphous oxide-based thin-film transistors (TFTs) have attracted considerable attention due to their higher field-effect mobility and good uniformity. Oxide-based TFTs such as IGZO TFTs can be fabricated at low temperature(less than 350 CÉ™) by simple process compatible to the commercially available Si:H TFTs fabrication process[1-7]. Therefore, amorphous oxide-based TFTs are considered as the pixel element for active-matrix liquid crystal displays and active-matrix organic light emitting diode displays. However, oxide-based TFTs are very sensitive to electrical stress and ambient condition such as light, temperature and moisture [8-12]. The changes in the characteristics of the TFT, such as the threshold voltage (Vth) shift, are caused by not only electrical and optical stress but also the atmospheric conditions. Especially, the electrical stress of oxide TFTs has been researched intensively and it is considered that the main reason of the Vth shift is charge trapping [10-11]. As for the light illumination, degradation under negative gate bias stress combined with light is reported because the TFTs are exposed to light and negative gate bias stress in display applications [8-9]. When light illumination is combined with negative gate bias stress, Vth is degraded more than that in the dark state and it is reported that hole carriers generated by light illumination contribute to charge trapping and accelerate the Vth shift [8-9]. However, the systematic analysis about the carrier concentration of active layer and the acceleration of Vth shift has not been accomplished yet. Suresh et al., have reported that as the carrier concentration of the active layer increases, the Vth shift increases under bias stress [10]. In this case, because the carrier concentration was controlled by the oxygen partial pressure for the deposition of the active layer, it is possible that not only the carrier concentration but also the other characte
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