A Study of Workfunction Variation in Pocket Doped FD-SOI Technology Towards Temperature Analysis
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ORIGINAL PAPER
A Study of Workfunction Variation in Pocket Doped FD-SOI Technology Towards Temperature Analysis Rameez Raja Shaik1 · G. Arun1 · L. Chandrasekar1 · K. P. Pradhan1 Received: 12 October 2019 / Accepted: 29 January 2020 © Springer Nature B.V. 2020
Abstract This paper focuses on a detailed study of workfunction variation to modulate the barrier height in fully depleted silicon on insulator (FD-SOI) technology including pocket doping. The work is further extended to evaluate the zero temperature coefficient (ZTC) point by varying the temperature for a wide range of 250K to 420K. The complete task is segregated into two parts according to the barrier height (φB ): (i) gate workfunction (φM ) is considered to be similar as that of semiconductor workfunction (φS ) (i.e., φB = φM −φS ≈ 0) (ii) φM is much higher than the φS (φB > 0). And, further the latter subsection is subdivided into DC and AC analysis for a better representation. The pocket design also checked by considering single sided as well as double sided to get more insightful advantages of the pocket design on FD-SOI technology by investigating wide range of electrical parameters in a comparative manner. From the analysis, it has been noted that the device having higher φB is outperformed in mitigating the leakage current. Hence, the work is further extended on the design with higher φB to evaluate the ZTC by observing the DC and AC parameters at different temperature ranges. All the device configurations are designed and analyzed through commercially available device simulator ATLAS. Keywords FD-SOI · Short channel effects · Floating body effects · Leakage · Barrier height
1 Introduction Silicon technologies are growing in a faster pace in every year by following the Moore’s law [1]. Rapid growth in chip speed and functional, has brought the MOSFET feature size into a nanometric scale. However, the nanometre MOSFETs suffer from a serious consequence i.e., short channel effects (SCEs) like hot-carrier effects (HCEs), drain-induced barrier lowering (DIBL) and threshold voltage (VT H ) roll-off [2]. Thus, further scaling of the silicon device relies on the so called SCEs [3, 4]. Rameez Raja Shaik
[email protected] G. Arun [email protected] L. Chandrasekar [email protected] K. P. Pradhan [email protected] 1
Department of Electronics & Communication Engineering, IIITD&M Kancheepuram, Chennai, 600127, India
One of the modern technology such as SOI is introduced to overcome the above mentioned SCEs [5]. Decrease in SCEs has given SOI MOSFETs to certain level of advantages over conventional bulk MOSFET. Hence, the comparative study of different SOI MOSFET over bulk MOSFET has already been demonstrated by many researchers [5–7]. However, the SOI MOSFETs are also suffering from certain problems due to its buried oxide layer like self-heating effects (SHEs) and floating-body effects (FBEs) [8–10]. SHEs in SOI are more prevalent than in bulk MOSFETs due to the presence of BOX layer, it is inevitable to analyze the temperature depen
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