Investigating linearity and effect of temperature variation on analog/RF performance of dielectric pocket high-k double
- PDF / 1,768,263 Bytes
- 8 Pages / 595.276 x 790.866 pts Page_size
- 17 Downloads / 197 Views
Investigating linearity and effect of temperature variation on analog/ RF performance of dielectric pocket high‑k double gate‑all‑around (DP‑DGAA) MOSFETs Vaibhav Purwar1 · Rajeev Gupta1 · Nitish Kumar2 · Himanshi Awasthi2 · Vijay Kumar Dixit1 · Kunal Singh3 · Sarvesh Dubey4 · Pramod Kumar Tiwari5 Received: 18 June 2020 / Accepted: 19 August 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract The present paper is about using three popular performance boosters in a device to battle with deterioration in device characteristics imposed by temperature variation. The dielectric pocket (DP) technology has been utilized in double gate-allaround MOSFET to limit the leakage current problem. Further, high-K dielectric as gate oxide is employed so that ON-state current may be improved with enhanced device scalability. The boosted immunity towards short-channel effects (SCEs) and improvement in the device’s analog performance is demonstrated through comparison between dielectric pocket high-K double Gate-All-Around (DP-DGAA) and double Gate-All-Around (DGAA) MOSFETs with temperature variation from 300 to 500 K by using commercially available ATLAS, a three-dimensional (3D) device simulator from SILVACO. Keywords Dielectric pocket · Double gate-all-around · High temperature · Linearity · Harmonic distortion · Analog/RF performance
1 Introduction CMOS downscaling has made the tiny transistors an indispensable part of our lives as they have been scaling-up the lifestyle of mankind since the last five decades. This fantastic journey made so far has been the eyewitness of advancements in integrated circuits (ICs) and system design, communication technologies, data storage technologies and reduced cost per function. In recent years, * Sarvesh Dubey [email protected] 1
Department of Electronics Engineering, Rajasthan Technical University, Kota 324010, India
2
Department of Electronics and Communication Engineering, Kanpur Institute of Technology, Kanpur 208001, Uttar Pradesh, India
3
Department of Electronics and Communication Engineering, National Institute of Technology, Jamshedpur, India
4
Department of Physics, L. N. D. College Motihari (B. R. A. Bihar University Muzaffarpur), Bihar 845401, India
5
Department of Electrical Engineering, Indian Institute of Technology Patna, Patna, India
several field-effect devices have been proposed for stable operation in extreme high-temperature conditions regarding applications in the nuclear power plant, automobile sensors, and spacecraft [1–4]. The high-temperature operating conditions put the practical restrictions of silicon led FETs rendering erratic outcomes such as a change in threshold voltage and drain currents with temperature. Therefore, the structural modifications in the MOSFET device structure to enhance the reliability of the device becomes obligatory. At present, multi-gate transistors [5–11] such as FinFETs [7–9] and Gate-All-Around (GAA) FETs [10, 11] are meticulously combating with the adverse challenges presented by SCEs becau
Data Loading...
