A Study on the Electronic Properties of Nitric Oxide Annealed MOS Structures Processed on 4H-SiC

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A Study on the Electronic Properties of Nitric Oxide Annealed MOS Structures Processed on 4H-SiC Kerlit Chew1, Chin-Che Tin2, Claude Ahyi2, Kim Nie Chong1, Meng Suan Liang1, Sir Cong Chong1, Rusli3, Kim Luong Lew1 1

Universiti Tunku Abdul Rahman (UTAR), Malaysia

2

Auburn University, U.S.A.

3

Nanyang Technological University, Singapore

ABSTRACT Interface state density profiling of the thermal oxide / n-type 4H-SiC interface which underwent post-oxidation nitric-oxide (NO) annealing showed that an interface state density of approximately 1×1011 cm-2eV-1 could be achieved at around 0.2 eV below the conduction band. It decreased exponentially by two orders to 1×109 cm-2eV-1 at around 0.9 eV from the conduction band. The values are comparable or better than other published work. The low interface state density achieved near the conduction band is important towards improved channel carrier mobility in SiC MOSFETs. A positive flat-band voltage shift of the SiC based MOS capacitor was also observed. The shift reduced under UV illumination. It could be attributed to slow acceptor-like (negatively-charged) traps, which may have contributed to the instabilities observed in drain current and threshold voltage suffered by SiC MOSFETs. INTRODUCTION MOSFETs based on (0001) Si-terminated face of 4H–SiC typically suffers from low inversion channel mobility (~ 10 cm2/V⋅s) far below their bulk electron mobility, attributed to the presence of interface states broadly distributed within 0.3 eV below the conduction band edge [1]. Studies have shown that passivation of oxide and interface traps by nitridation are effective to improve the interface quality. The nitrided oxides can be produced by post-oxidation annealing in nitric oxide (NO) or nitrous oxide (N2O) gas [2,3,4]. This paper will present a study on the distribution of interface state density as a function of energy within the n-type 4H-SiC bandgap at the thermal oxide/SiC interface for MOS samples underwent post-oxidation NO anneal. High frequency capacitance-voltage (C-V) and conductance-frequency (G-ω) measurements showed quite different results and possible reasons of the discrepancies will be explained. The results showed a density of approximately 1×1011 cm-2eV-1 was acheived at around 0.2 eV below the conduction band, which is comparable or better than some other published work [5,6,7,8]. This study also investigated the flat-band voltage shifts observed in our NO annealed MOS samples. Analysis showed that the shifts could be attributed to charged traps. The presence of these slow but mobile traps could have contributed to the instabilities in the drain current and threshold voltage in SiC MOSFETs discussed in some publications [9,10,11].

EXPERIMENTAL DETAILS The 4H-SiC wafers were made by Cree. It had an n-type substrate of resistivity 0.02 Ω-cm, a thin 0.50 µm n-type buffer layer with a doping density of 1×1018 cm-3 and a 10.39 µm thick lightly-doped n-type epilayer. Its doping density was 1.1x1015 cm-3, as deduced from our Schottky diode current-voltage measure