A three dimensional self-folding package (SFP) for electronics
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A three dimensional self-folding package (SFP) for electronics Jeong-Hyun Cho,1 Steve Hu,1 and David H. Gracias 1,2 1 Department of Chemical and Biomolecular Engineering and 2Department of Chemistry, Johns Hopkins University, 3400 N Charles Street, Baltimore, MD 21218, USA. ABSTRACT We describe the concept of a 3D self-folding package (SFP) for sensors and electronic devices. The strategy is based on a self-assembly strategy wherein 2D panels interconnected with hinges spontaneously fold-up when they are released from the substrate; self-folding can be triggered by temperature or selected chemicals. The strategy enables packaging of devices in porous polyhedral geometries that can either be untethered or substrate-bound. Self-folding can enable packaging of devices in small 3D form factors and may enable efficient cooling due to porosity. The utilization of this self-folding platform to enable 3D packaging of cantilever sensors and magnetic field sensitive strain gauges is summarized. INTRODUCTION As the complexity of electronic devices increases, the number of interconnected devices also increases and new strategies are needed to package them efficiently. These advances are directed at reducing interconnect distances and form factors, enabling efficient cooling, and allowing for highly interconnected devices. Conventional packaging of multiple die utilizes an inherently 2D approach (Fig. 1a); this approach has developed primarily due to the ease of multilayer lithographic patterning of device, interconnect, and packaging layers.
Figure 1 A comparison of packaging profiles. (a) Present-day packaging of five die in a 2D layout. (b) Stacking enables packaging with a small form factor but has relatively poor thermal characteristics, especially as the number of chips increases. Moreover, the stacking process is serial and can considerably increase processing steps. (c) Self-folding polyhedra enable parallel packaging of the devices in 3D with small form factors and with efficient cooling due to porosity.
Recently, there has been considerable interest in stacking die (Fig. 1b) to reduce overall form factors and decrease inter-device connection lengths. This approach typically utilizes a wafer bonding approach. However, there are some challenges with this approach especially as
the number of stacked devices increases. Firstly, wafer bonding is challenging especially when sub-micron alignment is required. Secondly, it is challenging to remove heat from stacked devices with multiple active layers. Finally, since the devices still have an inherent 2D geometry, it is challenging to create highly interconnected devices. We have been exploring an alternate approach depicted in Fig. 1c. Here, devices are packaged on the surfaces of hollow polyhedra using a self-folding approach which is highly parallel and can be applied across length scales. In our laboratory, polyhedra ranging in overall size from 100 nm to 2 mm have been demonstrated. Additionally, the polyhedra can be composed of metals, semiconductors, diel
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