Advances in the CMP Process on Fixed Abrasive Pads for the Polishing of SOI- Substrates with High Degree of Flatness
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Advances in the CMP Process on Fixed Abrasive Pads for the Polishing of SOISubstrates with High Degree of Flatness Martin Kulawski1; Hannu Luoto1; Kimmo Henttinen1; Ilkka Suni1; Frauke Weimar2; Jari Mäkinen3 1 :VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland 2 :3M Deutschland GmbH; Carl-Schurz-Str.1; D-41453 Neuss; Germany 3 :Okmetic Oy; Piitie 2; P.O. Box 44; FIN-01301 Vantaa; Finland Contact: [email protected] ABSTRACT The new approach using Fixed Abrasive (FA) pads for polishing thick film Silicon-onInsulator (SOI) wafers after bonding and grinding process [1] has been further developed. The aim is a practicable industrial manufacturing process, where the major specifications especially in long term stability and removal rate should be achieved. In base line studies a stable removal rate on suitable level has been reached, while the degeneration of the total thickness variation (TTV) was limited to a clearly smaller value than that being typical for the standard stock removal polishing. The overall removal in these tests was adjusted to 2-3 µm, which removes all sub surface damage (SSD) from wafers ground by ultra fine grinding wheels with very small average abrasive particle size. The process has been able to remove all visible grindlines after removing less than 1.5 µm. In another test with a further developed high density FA pad, removal rates up to ~0.6 µm/min were achieved. The polished samples were further processed and characterized by capacitive thickness measurements gauges, optical surface inspection tool (“Magic mirror”), atomic force microscopy (AFM) and optical reflection measurements. INTRODUCTION The manufacturing of thick film silicon-on-insulator (SOI) substrates currently faces a limitation when concerning low TTV values. While grinding tools are able to provide wafers with flatness values of less than 0,5 µm TTV, the subsequent polishing needed for removing the grindlines as well as SSD often degenerates the wafers to a level above 1 µm TTV. This is caused first by the high amount of material removal needed in order to remove all damage and residues from conventional grinding and second by the inability of conventional polishing to take care of the special edge shape formed during the SOI manufacturing process. A strong emphasis to round the edge of the SOI device layer can be seen. Together with the general non-uniformity of the process this results in elevated TTV values when applying the often required stringent edge exclusion of 3 mm based on the handle wafer diameter. Due to the required edge grinding of the upper device wafer this often leads to an actual edge exclusion of only 1 mm to be met for the CMP processing. The introduced combination of grinding with ultra fine wheels leading to low SSD and the use of FA pads leads to strongly reduced material removal being needed by polishing on the one hand and to greatly increased uniformity due to the extreme good capability of FA pads for planarization and uniform removal on the other hand.
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