Integration of CMP Fixed Abrasive Polishing into the Manufacturing of Thick Film SOI Substrates
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Integration of CMP Fixed Abrasive Polishing into the Manufacturing of Thick Film SOI Substrates Martin Kulawski1; Hannu Luoto1; Kimmo Henttinen1; Tommi Suni1; Frauke Weimar2; Jari Mäkinen3 1 :VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland 2 :3M Deutschland GmbH; Carl-Schurz-Str.1; D-41453 Neuss; Germany 3 :Okmetic Oy; Piitie 2; P.O. Box 44; FIN-01301 Vantaa; Finland Contact: [email protected] ABSTRACT The specification for the total thickness variation (TTV) of the device layers on thick-film silicon on insulator (SOI) wafers tighten for future applications. Therefore, the bulk removal polishing process of current technology after grinding cannot meet the demands in terms of flatness. The currently required amount of material removal for polishing out the induced sub surface damage (SSD) of the grinding is very high. Additionally, slurry-based CMP processes show unsatisfactory grindline and topography removal. This in turn reflects negatively to processing times, throughput and overall flatness performance. Encouraging early results of FA pad use for silicon and SOI polishing have already been further developed [1]. Low SSD grinding has been introduced to silicon manufacturing [1]. In this work, an integrated manufacturing process sequence is presented. Starting from low SSD grinding of the bonded SOI wafer couple, an optimized FA CMP step is replacing the conventional bulk polishing with reduced removal. The SSD after FA CMP is investigated by oxide induced stacking fault (OISF) method [2] and results are used to adjust the final polishing step of the substrates. The overall process sequence is highly advantageous in terms of performance in TTV and provides a highly competitive and effective method for achieving best possible surface quality with minimized total silicon removal. This method is not only useful for SOI wafers but also in other areas of silicon processing. INTRODUCTION When making thick film SOI substrates a significant amount of mechanical treatment on wafers has to be done. Unlike in thin film SOI the device layer of the wafer has to be formed by removing most of the bonded top substrate during grinding and subsequent polishing. Grinding is used to adjust the required thickness, which can vary from 1 µm to more than 100 µm. Grinding leads to very flat wafers, however it leaves not only mechanical abrasion lines, but also introduces a several microns deep layer with crystalline defects [4, 5]. Therefore, subsequent polishing is needed to provide a smooth and defect-free device layer surface. Conventional slurry-based CMP leads to unsatisfactory results in terms of TTV, as the edge of the slightly smaller device layer is rounded under the removal of the damaged layer. As the required polishing amount is increasing, the TTV degenerates. Currently a polishing removal of 5 µm is needed for slurry-based CMP to remove all grindlines and 6 to 8µm is necessary to remove all crystalline damage from standard grinding processes [1].
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For achieving flat thick
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