A Novel CMP Process on Fixed Abrasive Pads for the Manufacturing of Highly Planar Thick Film SOI Substrates
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A novel CMP Process on Fixed Abrasive Pads for the Manufacturing of highly planar thick film SOI Substrates Martin Kulawski1; Kimmo Henttinen1; Ilkka Suni1; Frauke Weimar2; Jari Mäkinen3 1 :VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland 2 :3M Laboratories (Europe); Carl-Schurz-Str.1; D-41453 Neuss; Germany 3 : Okmetic Oy; Sinimäentie 12; P.O. Box 44; FIN-01301 Vantaa; Finland Contact: [email protected] ABSTRACT A new approach using Fixed Abrasive (FA) pads has been undertaken to overcome the problem of non-uniform thick film Silicon-on-Insulator (SOI) wafers after CMP polishing. The theoretical models indicating the advantages of the 2-body system of the fixed abrasive configuration vs. the conventional 3-body system of slurry based polishing have been convincingly demonstrated in practise upon experiments in a wide range of parameters. As a result it is possible to maintain or improve the flatness of wafers after back grinding, while simultaneously removing the sub-surface damage. A surface quality of prime wafers can be reached on the device layer. Capacitive thickness measurement scans and atomic force microscopy (AFM) monitoring confirm the results. A detailed comparison with conventional processing has been carried out to clarify the advantages on bulk silicon wafers. Decoration etching is used to analyse the wafer surface quality in terms of oxide induced stacking faults (OISF). As a result an alternative processing method is proposed for manufacturing thick film SOI substrates with improved uniformity.
INTRODUCTION The manufacturing of thick film silicon-on-insulator (SOI) substrates requires a significant amount of mechanical treatment. In thin film SOI production the SmartCut™ process leaves an already highly uniform surface, which only requires a small amount of polishing if at all [1]. Processing of thick film SOI however requires extensive grinding and polishing to remove most of the bonded device wafer. Therefore, care has to be taken for the non-uniformity of the thinning processes. While grinding leads to a TTV (Total Thickness Variation) of 0,5 µm on the wafer it leaves a sub-surface damage (SSD) of up to 6 µm deep in the substrate, which has to be removed by subsequent chemical mechanical polishing (CMP). The conventional slurry based processing however often leads to high values of thickness non-uniformity due to the strong bias for rounding the edge of the thick device layer with reduced diameter on top of the handle wafer. Since the specs for SOI-wafers at the time are more and more demanding with TTV values of < 0,5µm at EE (Edge Exclusion) of < 3mm, the conventional processing for highly planar SOI wafers often results in low yields or is not working at all. To overcome this obstacle polishing of ground wafers on so-called fixed abrasive (FA) pads has been investigated in order to improve the CMP process performance and maintain the flatness of the SOI substrate.
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