Amorphous Silicon and Silicon-Germanium Thin-Film Transistors Formed by Ion Implantation
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Amorphous Silicon and Silicon-Germanium Thin-Film Transistors Formed by Ion Implantation G. Sarcona*, M. K. Hatalis*, and A. Catalano*.' * Sherman-Fairchild Laboratory, Electrical Engineering Dept,
Lehigh University, Bethlehem, PA 18015 Solarex Corporation, Newtown, PA.
ABSTRACT Thin-film, n-channel transistors were fabricated in hydrogenated amorphous silicon and silicongermanium thin films using ion implantation to form source and drain regions. The germanium alloy content in the films were: 0, 15, and 25 at%. For each content of germanium, the annealing temperature and time necessary to activate the implant, without degrading device performance due to hydrogen effusion, was determined. The time necessary to anneal aluminum to form ohmic contacts at the optimal anneal temperature (2600C) was also determined. Thin-film transistors were characterized, and important device parameters such as: saturation mobility, threshold voltage, subthreshold swing, and ON-OFF current ratio were determined.
Introduction Research in amorphous semiconductors has been increased by the utility of thin-film devices in imaging and display applications [1-4]. Amorphous devices are compatible with the low temperature processing requirements of commercial glasses [5]. Although amorphous silicon is already in use for displays [1], amorphous silicon-germanium has many advantages over amorphous silicon. The bandgap is tunable by the content of germanium, making the material useful for solar cells [2] and image sensors [3]. Amorphous silicon-germanium is more resistant to light-induced defects (Staebler-Wronski effect) [4], exhibits a lower density of gap states [6], and activates dopant impurities [4] more rapidly than amorphous silicon. Research in amorphous silicon-germanium thin-film devices has been limited [7]. In this paper, amorphous silicon and silicon-germanium thin-film transistors (TFTs) are fabricated using ion implantation to delineate the source and drain regions, instead of deposited highly-doped contact layers [8] which increase processing complexity. This eliminates the potential for an interfacial region between the device layer and the contact layer, which has been shown to produce poor device performance [8]. Devices are compared by their subthreshold swing, threshold voltage, electron saturation mobility, and the ON-OFF currents and their ratio. In order to fabricate devices at low temperature, the critical process steps of activation annealing and contact sintering were examined for their time and temperature constraints.
Experimental Hydrogenated amorphous silicon and silicon-germanium films of various alloy content were deposited by plasma-enhanced chemical vapor deposition on 1000 A thermally-grown SiO 2 . The amorphous film thickness varied across the wafers, but averaged 600 A. With photoresist on the device side, the back oxide was etched in HF since the substrate served as the gate electrode. Islands were defined by plasma etching in SF6. The source and drain regions were doped by ion implantation while the ch
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