An Analytic Model for Predicting Single Event (SE) Crosstalk of Nanometer CMOS Circuits
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An Analytic Model for Predicting Single Event (SE) Crosstalk of Nanometer CMOS Circuits Baojun Liu 1
&
Li Cai 2 & Xiaoqiang Liu 2
Received: 3 September 2019 / Accepted: 18 June 2020 # Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract With the technology node scaling down into nanometer range, the effect of parasitic inductance and capacitance between the interconnect lines on predicting single event crosstalk (SEC) has to be considered. An analytical model is proposed to evaluate SEC in nanometer CMOS circuits based on the equation circuit of single event transient and RLC distributed model of interconnect. The transfer function of the arbitrary segment of interconnects is deduced by applying KCL and KVL laws in Laplace domain. The accurate expression of SEC voltage is achieved by the operation of matrix polynomial. For convenient calculation, a third-order exponential model is used to describe the SEC voltage approximately. The simulation results at the technology nodes of 22 nm, 32 nm, 45 nm, 65 nm, and 90 nm show that in comparison to previous work, the analytical model has a significantly improved accuracy with an average error of only 2.19%. Keywords Single event crosstalk . Nanometer . Analytic model
1 Introduction Single event transient (SET) could be created when an energetic particle, especially alpha particles, strikes the sensitive area within a combination circuit [1–3]. If a SET propagates to a flip-flop or other memory elements, it may induce a soft error, which has become a growing concern in nanometer CMOS technologies [3–5]. Advances in modern technology scaling cause decreasing space and increasing thickness to width ratio of interconnects, which contribute to increasing the crosstalk effect between the interconnects [5–7]. As device feature size scaled down, SET generated on a circuit node may affect multiple logic paths due to the crosstalk effect among interconnects. It will increase the vulnerable parts of the circuit and will increase its SET susceptibility [6, 7]. Therefore, single event Editorial Responsibility: V. Champac * Baojun Liu [email protected] 1
Aviation Maintenance NCO Academy, Air Force Engineering University, XinYang 464000, HeNan, China
2
Department of Basic Science, Air Force Engineering University, Xi’An 710051, ShannXi, China
crosstalk (SEC) effects between the interconnect wires should be considered in the early stages of the today chip design flow and signal integrity for application to space and ground radiation environments [5, 6, 8, 9]. Therefore, the prediction of SEC has been an important design concern. Previously many analysis techniques and methods had been presented for predicting crosstalk voltage [5, 6, 8–17], such as finite difference time domain (FDTD), ABCD matrix methods, and so on. These methods are time consuming, memory intensive, or prediction inaccurate. Although SPICE produces very accurate results, it is computationally expensive to be used at the full-chip level. With the feature size of CMOS device scaling
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