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Analog IC Reliability Simulation

5.1 Introduction In Chap. 4, an overview of existing reliability simulators has been given. Although a lot of research has been conducted in this area, leading to the implementation of a reliability simulation framework in each of the major commercial SPICE simulators, there are still a lot of deficiencies remaining (also see Sect. 4.4). Especially with the evolution to ever-smaller CMOS devices, statistical effects resulting from process variations and stochastic aging effects become more and more important. On top of that, most academic and commercial simulators are limited to the simulation of rather small circuits. Accurate reliability evaluation of large analog or mixed-signal circuits is therefore still not possible. In this chapter a set of simulation methods, addressing these problems and other issues listed in Sect. 4.4, is proposed. The focus of the proposed simulator is on the simulation of analog circuits, although the methods can also be applied to small to medium-sized digital blocks. Section 5.2 first discusses an implementation of a deterministic reliability simulator. Such a simulator does evaluate the impact of transistor aging on the performance of the circuit, but does not include stochastic effects such as process variations or stochastic aging effects. The proposed method includes some techniques to achieve a good simulation accuracy while limiting the computational effort. The combined impact of multiple aging effects on a single transistor is also included. Further, a sensitivity analysis allows circuit weak spot detection and provides a designer with the necessary knowledge to design a more reliable circuit. Then, Sect. 5.3 discusses two implementations of a stochastic reliability simulator. This simulator includes the impact of stochastic effects and enables the capability to analyze the time-to-failure distribution of a design. A first implementation uses a brute-force Monte-Carlo approach which proves to be accurate but very computationally intensive. A second implementation using a response surface method is much more efficient. The latter also provides the user with an analytical model of the circuit performance as a function of the most important statistical parameters. The response surface method proves to be 1–3 orders of magnitude faster compared E. Maricau and G. Gielen, Analog IC Reliability in Nanometer CMOS, Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-6163-0_5, © Springer Science+Business Media New York 2013

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5 Analog IC Reliability in Nanometer CMOS

to the MC-based implementation. Finally, Sect. 5.4, proposes a flow to accurately simulate the impact of deterministic and stochastic aging effects on large analog and mixed-signal circuits. This method uses a hierarchical approach. First, the system is partitioned in system subblocks. Then, each subblock is modeled separately and finally the combined effect on the entire system is calculated using these subblock models. An innovative active learning sample selection st