Analysis of Nanotopography in Silicon Generated by the Polishing Process
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Analysis of Nanotopography in Silicon Generated by the Polishing Process Hiromichi Isogai and Katsuyoshi Kojima TOSHIBA CERAMICS CO., LTD., Silicon Company, Wafer Processing Technology 6-861-5 Higashikou Seiroumachi Kitakanbaragun Niigata Prefecture, Japan ABSTRACT This paper describes a new model, which analyzes the effects of the polishing conditions on nanotopography after polishing silicon (Si) substrates. The thickness uniformity of dielectric oxide-films after Chemical Mechanical Polishing (CMP) is affected by nanotopography of the Si substrate. Therefore, reducing nanotopography in Si substrates is essential in order to obtain highly uniform dielectric film thickness after CMP. We have developed a model based on Preston’s equation for estimating the change in nanotopography of Si substrates due to polishing. In this model, various conditions relating to the structure of the polishing apparatus, the polishing pad material and the motion of the substrate can be taken into consideration. To investigate the influence of the polishing conditions on nanotopography, we compared experimental polishing results with calculations using this model. Thus, it was clarified that the generation of nanotopography in the polishing process that determines the final shape of the substrate, depends on the history of the pressure and contact distance produced during the process. INTRODUCTION To improve the planarity and thickness uniformity of dielectric films after Chemical Mechanical Polishing (CMP), the nanotopography of the Si substrate needs to be decreased [1-4]. However, no detailed reports on the mechanisms that generate nanotopography in the wafer manufacturing process have been published. As for CMP, there are some reports on material removal models based on Preston’s equation and analysis using Finite Element Methods (FEM) [5-10]. In this work, we have developed a model based on Preston’s equation for estimating the changes in nanotopography during Si substrate polishing that determine the final shape of the substrate. First, a numerical model for simulating the change in the global shape of a Si substrate in the polishing process was developed using FEM. Comparisons between the numerical model and experimental results were performed for two different kinds of carrier structure, and the validity of the model was verified. Next, the influence of the carrier structure on nanotopography was clarified by including in the model the undulating shape of the Si substrate before polishing. Furthermore, it was shown that the groove pattern of the polishing pad affects the nanotopography of the substrate. EXPERIMENTAL Global shape model Schematic diagrams of the polishing apparatus and the two kinds of carrier used are shown in figure 1. The polishing apparatus is the rotary type that is commercially available and generally widespread. Figure 1 (b) indicates one method in which the substrate is attached to a vacuum chuck made of alumina and the chuck is pressurized by an air bag. The other method, shown in figure 1 (c), ha
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