Annealing of Nanocrystalline Silicon Micro-bridges with Electrical Stress
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1144-LL03-25
Annealing of Nanocrystalline Silicon Micro-bridges with Electrical Stress Gokhan Bakan1, Adam Cywar1, Cicek Boztug1, Mustafa B. Akbulut1, Helena Silva1 and Ali Gokirmak1 1
Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Way, Storrs, CT 06269, USA ABSTRACT Nanocrystalline silicon (nc-Si) micro-bridges are melted and crystallized through Joule heating by applying high-amplitude short duration voltage pulses. Full crystallization of nc-Si bridges is achieved by adjusting the voltage-pulse amplitude and duration. If the applied pulse cannot deliver enough energy to the bridges, only surface texture modification is observed. On the contrary, if the pulse is not terminated after the entire bridge melts, molten silicon diffuses on to the contact pads and the bridge tapers in the middle. Melting of the bridges can be monitored through current-time (I-t) and voltage-time (V-t) measurements during the electrical stress. Conductance of the bridges is enhanced after the electrical stress. INTRODUCTION Thin-film transistors (TFTs) are one of the major components in large-area electronics [1]. Imaging and sensor arrays such as active matrix liquid crystal displays and x-ray imagers use TFTs as switches and in peripheral circuitry [1]. Amorphous silicon (a-Si) is commonly used as TFT material for reliable and cost-effective large-area electronics applications. Although a-Si has very low electron mobility [2], it has the advantage of uniform and low-temperature processing which may also provide the opportunity of using flexible materials like plastics as the substrate [3]. Interest in the studies of the silicon crystallization methods has increased in last several decades due to low processing temperature requirements and demand for high performance TFTs[2, 4]. In this work, crystallization of nanocrystalline silicon (nc-Si) bridges by electrical stress [5] is studied as a silicon crystallization method. Nc-Si films are deposited on a thermally grown oxide in a low-pressure chemical vapor deposition (LPCVD) system with high-level phosphorous doping (~5x1020 cm-3) [6]. Nc-films are patterned as wires with large contact pads using photolithography and reactive ion etching (RIE). Nc-Si wires are released from the underlying oxide using buffered oxide etch to form bridges. As fabricated bridges have lengths ranging from 0.5 to 5 µm and widths in the order of 0.5 µm. EXPERIMENT and DISCUSSION Large-amplitude short-duration square voltage pulses are applied across the nc-Si bridges by making contact with large nc-Si pads using tungsten probes. Applied voltage and the corresponding current through the bridges are monitored by a high-speed oscilloscope as shown in Figure 1.
Figure 1. Circuit schematic of the experimental setup, where Rc is the contact-pad resistance. IV characteristics of the bridges are measured by the parameter analyzer before and after the electrical stress. Switch box switches to pulse generator unit to apply the voltage pulse. Applied voltage pulse amplitude and current t
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