Application of FIB/SEM and TEM to Bit Failure Analyses in SRAM Arrays
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A5.77.1
Application of FIB/SEM and TEM to Bit Failure Analyses in SRAM Arrays Wentao Qin, Alex Volinsky1, Larry Rice, Lorraine Johnston and David Theodore Digital DNATM Labs, Motorola MD EL622, 2100 E Elliot Road, Tempe, AZ 85284 1
Department of Mechanical Engineering, University of South Florida, Tampa FL 33620
ABSTRACT Many microelectronic chips contain embedded memory arrays. A single SRAM bit-cell contains several transistors. Failure of any of the transistors makes the entire bit-cell inoperable. Dual-beam Focused Ion Beam (FIB) combines the slicing capability of FIB with in-situ SEM imaging. The combination offers unparalleled precision in looking for root causes of failures in microelectronic devices. Once a failure site is located, an FIB lift-off method can be used to prepare a TEM sample containing the area of interest. Further structural, elemental information can then be acquired from the failure site. We report here analyses of single and multiple bit failures in SRAM arrays carried out using FIB/SEM, and in two cases TEM imaging and EDS/PEELS. Root causes of bit failures including remnant seed-layer metal between stacked vias have been identified. INTRODUCTION With the advantages of high access-speed and virtually unlimited read-write endurance, SRAM has become a prevalent memory on the market. On the other hand, it is well-known to for its sensitivity to process variation. Therefore SRAM is also frequently used as a qualification vehicle for process development. As a result, failure analysis of SRAM chips is critical not only for trouble-shooting and problem-solution, but also for assurance of on-time delivery to market. Several failure mechanisms of SRAM bits have been reported in literature, including up-shift of threshold voltage and decrease of trans-conductance of the Ld-PMOS due to local depletion in the polySi gate [1], node-to-node and node-to-power-line shorting through CMP scratches [2], electrical opens caused by dangling contacts at bitline and PMOS [3, 4], and bridging of W-plugs through W-extrusion [3]. In all of these cases the feature sizes are on the order of a tenth of a micron or larger. In the scaling–down of microelectronics, reduction in device-sizes can increase their sensitivity to process variation. Root causes of failures can be very subtle and localized to extremely small size scales. We report here, failure analyses involving characterization of tiny features down to the size scale of 1 nm. EXPERIMENTAL DETAILS Failing bits were identified electrically in memory arrays, and subsequently located by a dual-beam Focused Ion Beam (FIB). In-situ SEM of the FIB was used to check for any abnormalities in the crosssection while material was being removed. In some cases SEM imaging and EDS (Energy-dispersive Spectroscopy) were sufficient to identify failure mechanisms once such abnormalities were revealed.
A5.77.2
However, there were occasions when the resolutions in SEM imaging and/or elemental analyses were inadequate. TEM (transmission electron microscopy) was subsequently
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