FPGA Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application
- PDF / 154,552 Bytes
- 10 Pages / 612 x 792 pts (letter) Page_size
- 67 Downloads / 158 Views
Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application Sayan Tripathi1*, Raj Kumar Maity2**, Jhilam Jana1***, Jagannath Samanta2****, and Jaydeb Bhaumik1***** 1
Jadavpur University, Kolkata, India Haldia Institute of Technology, Haldia, India *ORCID: 0000-0001-5459-6151, e-mail: [email protected] **ORCID: 0000-0002-2676-3052, e-mail: [email protected] ***ORCID: 0000-0002-4507-2521, e-mail: [email protected] ****ORCID: 0000-0003-1168-1166, e-mail: [email protected] *****ORCID: 0000-0001-5382-9128, e-mail: [email protected] 2
Received September 16, 2019 Revised June 14, 2020 Accepted October 1, 2020
Abstract—Mostly random and adjacent error correcting codes are used to protect stored data in SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an important issue related to the reliability of static random access memories (SRAMs). As a result, multiple adjacent bits of a memory are distorted and valuable information is lost. To mitigate these problems, multi-bit adjacent error correcting codes are preferable in SRAM. In this paper, single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are proposed. The performances of the proposed SEC-DED-DAEC codes are observed in terms of area and delay. Theoretical area overhead of proposed codes is at most 49.98% lower compared to the related design. Also the proposed design has around 28.79% lesser critical path delay compared to existing design. The best improvement achieved in terms of number of look-up table (LUT) and delay are 22.69 and 29.98% respectively compared to other existing codes in FPGA platform. The proposed codes can be used in embedded SRAM applications. DOI: 10.3103/S0735272720100040
1. INTRODUCTION Static random access memories (SRAMs) are employed to store digital information in memory cells which retain information as long as its power is on. The major concern for SRAM is soft errors which are caused by radiation [1], [2]. These soft errors corrupt the information stored in memory cells [3]–[7]. Recently, multiple bit upsets (MBUs) happen frequently in memories due to scaling in CMOS technology. So to enhance the reliability of the memories, errors must be detected and corrected efficiently. Single error correction (SEC) codes [8], [9] are commonly used to protect memory cells when only one bit memory cell is affected by soft error. Alternatively, Bose–Chaudhuri–Hocquenghem (BCH) code [3], [10] and Reed Solomon (RS) code [11]–[13] can protect MBUs with higher decoding complexity. Recently various adjacent error correcting codes [3], [6], [14]–[16] are already introduced to detect and correct adjacent errors in SRAMs. The simplest form of adjacent ECCs are termed as SEC-DED-DAEC codes which have considerable latency and area overhead in different applications [17]–[20]. Dutta et al. presented the new approach of adjacent error correction codes for memories [7]. These SEC-DED-DAEC codes need lower area compared to SEC-DED co
Data Loading...
