Applications of MeV Ion Implantation in Semiconductor Device Manufacturing (Invited Paper)
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ABSTRACT Use of MeV ion implantation for mass production of CMOS devices at 0.Spm design rule and beyond is now being accepted around the world for 16Mb DRAM, 16Mb Flash memory and CMOS logic/microprocessor technologies. Incorporating MeV well formation for twin well and triple well results in a reduction of up to 3 masking layers corresponding to process simplification and manufacturing cost reduction of 10% to 16%. For CMOS logic application, a new structure called BILLI (BuriedImplanted Layer for Lateral Isolation) is showing great promise for latch-up free CMOS and when combined with hydrogen denuded bulk Czochraliski (CZ) grown silicon wafers, has the potential to replace epitaxial wafers with improved device performance. This paper will review MeV ion implantation use for these various CMOS applications.
INTRODUCTION With the transition from 150mm to 200mm wafers, MeV implantation is being used for replacement of high temperature (I 100TC to 1200'C) diffused well formation techniques with low temperature/low thermal budget MeV well formation techniques (800 0C to 900oC). In the case of triple well formation, diffusions one to two days long have been required to drive-in deep n-wells or p-wells 4pm to 6pum deep. Besides reducing wafer thermal stress, MeV well formation also reduces twin well fabrication by 2 to 3 masking layers and 16Mb DRAM manufacturing complexity and costs by 10% has been reported and is shown in Fig.1 [1-7]. For triple well, Tsukamoto reported a 4-mask process (replacing 6-mask diffused process) using implant energies up to 3MeV for low voltage 3.3v 16Mb DRAM manufacturing shown in Fig.2 [4]. Mask # 1 2
I
Standard MeV Twin MeV BILLI Twin Diffused Well lRetrograde Well Retrograde Well n-well
Field oxide
Field oxide
Field oxide
n-well
n-well
p-well channel stop
pwell
n-well channel
stop/V¢ Implant
5 Total Masks
p-well VT implant 5
3
2
Fig. 1: Masking layer process comparison between diffused and MeV twin well formation. 123 Mat. Res. Soc. Symp. Proc. Vol. 354 0 1995 Materials Research Society
M1
LOCOS Formation
M2
Bottom n-layer
P 3 MeV
M3
n-well &PMOS V,
Cluster11 1) P 1.0 MeV 2) P 450 keV 3) P 60 keVor 8 30 keV (Opt)
M4
-p
p-well & NMOS V,
N,,s
Cluster I1 I) B o00 keV
44ub.
P
well
ZPweu
p- sub.
2)B250keV 3) B 30 keV (Oplional)
Fig.2: 4-masking layer process for an MeV triple well structure. From a device point of view, MeV implant technology allows precise positioning and control of dopants and junctions with minimal vertical and lateral diffusion. Reported improvements in device characteristics include: junction leakage, soft error rate, latch-up immunity, DRAM retention time and reduction in single bit failure [1,4,7]. At the circuit level, improved low voltage operation, operating speed, flash chip size reduction 30% to 50% and overall increase in circuit yields have also been reported [4,6]. APPLICATIONS TO TWIN AND TRIPLE WELL FORMATION
Twin Wells MeV twin retrograde well formation VMW (Vertically Modulated Well) doping profiles are shown in Figs
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