Atomic-scale investigation of the dielectric screening at the interface between silicon and its oxide
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Atomic-scale investigation of the dielectric screening at the interface between silicon and its oxide Feliciano Giustino and Alfredo Pasquarello Institut de Th´eorie des Ph´enom`enes Physiques (ITP), Ecole Polytechnique F´ed´erale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland, and Institut Romand de Recherche Num´erique en Physique des Mat´eriaux (IRRMA), CH-1015 Lausanne, Switzerland ABSTRACT We investigate the dielectric screening across the Si-SiO2 interface using a first-principle approach. By determining the profile of the microscopic polarization and the effective polarizabilities of SiOn (n = 0, ..4) structural units, we show that the variation of the local screening across the interface relates to the chemical grading. The oxide region near the Si substrate shows the same dielectric permittivity as bulk SiO2 as long as the oxide is locally stoichiometric. The suboxide region carries an enhanced permittivity, with a value intermediate between those corresponding to bulk Si and SiO2 . The implications of these findings for the scalability of the equivalent oxide thickness in high-κ gate stacks are discussed. INTRODUCTION Large-scale circuit integration relies upon the ability of reducing the channel length in complementary metal-oxide-semiconductor (MOS) devices while maintaining a high capacitance density in the gate insulator. The capacitance requirement could in principle be met by reducing the insulator thickness, but it is well known that the natural oxide SiO2 leads to unacceptable levels of leakage current when it is thinner than about 1.3 nm [1]. Since the targeted equivalent oxide thickness (EOT) for next generation transistors falls below 1 nm, a huge effort is ongoing to replace SiO2 with an alternative gate dielectric of higher permittivity κ such as ZrO2 , HfO2 and their silicate and nitride alloys [2]. One major issue in this research area concerns the formation of an interfacial SiO2 layer between the silicon substrate and the high-κ material during deposition. While beneficial in terms of reduced interface defect density, this low-κ interlayer sets a lower bound to the EOT of the overall stack (EOTstack = EOTinterl + EOThigh−κ ). To date however, it is not yet clear whether the EOT of the interlayer equals its physical thickness (as occurs if κinterl = κSiO2 = 3.9) or is somewhat reduced by an enhancement of its permittivity [1,3]. This question is crucial for assessing the scalability limit of MOS devices. While a direct experimental answer to this question is complicated by the difficulty of accessing the local dielectric behavior of a buried layer [4], a first-principles approach is best suited to study these atomic-scale properties. In the following we report on both the static and high-frequency local dielectric screening at the Si-SiO2 interface. We show that the oxide permittivity increases near the substrate, and we trace this behavior back to the role of partial oxidation states of silicon. THEORY To model the SiO2 interlayer we consider a Si-SiO2 superlattice with a 2×2 interface S
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