Back Gate Effects in N-Channel Monocrystalline Silicon Devices-on-Glass and their Suppression by Boron Ion Implantation
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Mat. Res. Soc. Symp. Proc. Vol. 558 @2000 Materials Research Society
can be suppressed by the inclusion of boron at the bond interface. Transistors fabricated on SOG layers with back gate suppression are described and their characteristics are compared with those without the boron implant. EXPERIMENT Silicon-On-Glass Fabrication The starting materials employed in the fabrication of the SOG layers were 100mm diameter p-type silicon wafers for the active substrate and 100mm diameter Coming code 1737 glass substrates for the handle substrate. The Coming code 1737 substrate has a maximum processing temperature of 6500C and a thermal coefficient of expansion, 37.8x10 7P/C. This expansion coefficient is closely matched to that of silicon. This is important in future temperature ramping cycles during processing. In order to reduce stress during bonding and to provide a barrier to glass impurities, a 0.5jtm thermal silicon dioxide layer was grown on the silicon substrate. Electrostatic bonding was performed at a temperature of 550'C with an applied voltage of 1000V for a period of 60mins resulting in void free bond formation. For the back gate suppression test layers, the silicon substrate was implanted with boron at an energy of 40keV with a dose of 7.4x10' 2cnf 2, prior to the growth of the 0.5gtm silicon dioxide layer. Electrostatic bonding performed using the above parameters, also resulted in a good quality bond. Figure 1, shows a birds eye image of the silicon/glass bond interface, looking through the transparent glass substrate. A good quality bond is observed. Both sets of substrates were thinned using precision grinding and polishing technology. The grinding step removed the bulk of the silicon substrate leaving a SOG thickness of 6ptm. The polishing step removed any damage caused by the grinding providing a final device quality SOG layer of thickness 1.5jim - 2gtm.
Figure 1: Birds eye image of the bond interface between the silicon dioxide layer and the glass substrate looking through the glass substrate.
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The boron implant conditions of implant energy: 40keV and implant dose: 7.4x1012cm-2 were chosen to give a threshold voltage shift of 8-1OV for a bond oxide growth of 0. 5Pm Transistor Fabrication Process Due to the temperature restrictions imposed by the glass substrate, a low temperature fabrication process was employed with the maximum temperature used during fabrication being 620'C. The transistors are self aligned polysilicon gate transistors with the gate, source and drain doped by ion implantation. Once the thin silicon-on-glass layers have been produced, the transistor fabrication follows the same procedure for both the standard and boron ion implanted layers. Firstly the SOG substrates, were patterned and reactive ion etched to form the transistor device islands. The gate dielectric layer, thickness 100nm, was subsequently deposited by Atmospheric Pressure Chemical Yapour Deposition(APCVD) at a temperature of 440TC using silane and oxygen. The quality of the layer was improved by densification
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