Bit Manipulation Accelerator for Communication Systems Digital Signal Processor
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Bit Manipulation Accelerator for Communication Systems Digital Signal Processor Sug H. Jeong School of Electrical and Computer Engineering, Ajou University, Suwon 443-749, Korea Email: [email protected]
Myung H. Sunwoo School of Electrical and Computer Engineering, Ajou University, Suwon 443-749, Korea Email: [email protected]
Seong K. Oh School of Electrical and Computer Engineering, Ajou University, Suwon 443-749, Korea Email: [email protected] Received 30 January 2004; Revised 14 November 2004 This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR (exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 µm standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about 40%∼80% for scrambling, convolutional encoding, and interleaving compared with existing DSPs. Keywords and phrases: bit manipulation, application-specific DSP, VLSI architecture.
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INTRODUCTION
With the rapid progress of communication technologies, various communication systems have been developed, such as xDSL (digital subscriber line), WLAN (wireless local area network), PLC (power-line communications), DMB (digital multimedia broadcasting), and IMT-2000 (International Mobile Telecommunications-2000). These communication systems require large computational power and low power consumption. Therefore, ASIC (application-specific integrated circuit) solutions have been widely used to implement these communication systems. However, conventional ASIC chips face several limitations such as lack of flexibility for various communication standards, high development costs, and slow time-tomarket. Thus, there have been strong demands to implement communication systems using programmable processors. Recently, the concept of the software defined radio (SDR) has been promoted [1]. SDR is a flexible communication system that supports multimode and multiband using programmable processors. Thus, implementation methods are changing from ASIC solutions to DSP (digital signal
processor) -based solutions that can have advantages in several aspects. Programmable DSPs are greatly improving time-to-market and allowing faster changes and upgrades than hardwired ASIC chips. Hence, the market of ASDSP (application-specific digital signal processor) compromising advantages of both ASIC and DSP is growing [2]. General communication systems consist of functional blocks, such as source coding, channel coding, modulation, synchronization, demodulation, channel decoding, and so forth. For example, Figure 1 shows the baseband processing of the WLAN OFDM (orthogonal frequency-division multiplexing) modem system [3]. The binary input data is scrambled and enc
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