VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems
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VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems Jen-Chih Kuo Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan Email: [email protected]
Ching-Hua Wen Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan Email: [email protected]
Chih-Hsiu Lin Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan Email: [email protected]
An-Yeu (Andy) Wu Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan Email: [email protected] Received 30 January 2003 and in revised form 10 July 2003 The technique of orthogonal frequency division multiplexing (OFDM) is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the fast Fourier transform (FFT) and inverse FFT (IFFT) operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of lowpower consumption. We also implement the twiddle factor butterfly processing element (PE) based on the coordinate rotation digital computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 µm 1P4M CMOS technology. The simulations results show that the chip can perform (64–2048)-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256 ∼ 2K), DAB, and 2k-mode DVB. Keywords and phrases: cached FFT, mixed-scaling and rotation CORDIC, and OFDM communications.
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INTRODUCTION
The orthogonal frequency division multiplexing (OFDM) system is a form of multicarrier modulation (MCM) technologies [1, 2, 3]. Due to its robustness against frequencyselective fading or narrowband interference, the OFDM technology has been widely implemented in many digital communications such as wireless local area network (WLAN, IEEE 801.11a/g), digital audio/video broadcasting
(DAB/DVB), asymmetric DSL (ADSL), and very-high-speed DSL (VDSL) systems [4, 5, 6]. The most important modulation/demodulation kernel in OFDM system is the fast Fourier transform and inverse FFT (FFT/IFFT) operations. However, the size and execute time, TFFT , of the FFT/IFFT pr
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