Capacitance-Voltage (C-V) Hysteresis in the Metal-Oxide-Semiconductor Capacitor with Si Nanocrystals Deposited by the Ga
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Capacitance-Voltage (C-V) hysteresis in the Metal-Oxide-Semiconductor capacitor with Si nanocrystals deposited by the gas evaporation technique Puspashree Mishra, Shinji Nozaki, Ryuta Sakura, Hiroshi Morisaki, Hiroshi Ono and Kazuo Uchida Department of Electronics Engineering, The University of Electro-Communications, Chofu-Shi, Tokyo-182-8585, Japan. ABSTRACT Capacitance-Voltage (C-V) hysteresis was observed in the Metal-Oxide-Semiconductor (MOS) capacitor with silicon nanocrystals. The MOS capacitor was fabricated by thermal oxidation of Si nanocrystals, which were deposited on an ultra-thin thermal oxide grown previously on a p-type Si substrate. The Si nanocrystals were deposited by the gas evaporation technique with a supersonic jet nozzle. The size uniformity and the crystallinity of the Si nanocrystals are found to be better than those fabricated by the conventional gas evaporation technique. The C-V hysteresis in the MOS capacitor is attributed to electron charging and discharging of the nanocrystals by direct tunneling though the ultra-thin oxide between the nanocrystals and the substrate. The flat-band voltage shift observed during the C-V measurement depends on the size and density of the nanocrystals and also on the magnitude of the positive gate bias for charging. The retention characteristic is also discussed. INTRODUCTION Recently, Metal-Oxide-Semiconductor field effect transistor (MOSFET) memories based on nanocrystals or quantum dots [1,2] have attracted considerable interest due to many possible advantages over the currently popular flash EEPROMs (Electrically Erasable Programmable Read-only memories). The memory operation is achieved through confinement of carriers in the nanocrystals as distributed floating gates and thus allowing the tunneling oxide to be thinner in comparison to that in the EEPROMs having continuos floating gate. Therefore, a number of benefits such as reduced hot carrier degradation, operation at lower voltages, low power consumption, faster write times and long retention time are observed in nanocrystal based memories. It is desirable that the nanocrystals have uniform size and shape and well separated from each other in order to achieve the ideal memory operation. Nanocrystal deposition by gas evaporation technique with a supersonic jet nozzle has been demonstrated earlier [3] and seems to meet the above requirement. In the present paper, we report the Capacitance-Voltage (C-V) characteristics of a MOS (Metal - Oxide – Semiconductor) capacitor containing Si nanocrystals deposited by the above technique and discuss the feasibility for possible non-volatile memory applications. EXPERIMENT AND RESULTS Figure 1 shows the apparatus of the gas evaporation technique with a supersonic jet nozzle. Si nanocrystals are deposited at supersonic speed, resulting from the differential pressure between the Si evaporation and deposition chamber. The nozzle of diameter 1/8 inch keeps the
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Substrate Deposition Chamber
Vacuum pump Clusters
Supersonic Jet Nozzle
BN Boat
Si
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