Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing
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Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing Takeo Matsuki, Yasushi Akasaka, Kiyoshi Hayashi, Masataka Noguchi, Koji Yamashita, Hideyuki Syoji, Kazuyoshi Torii, Naoki Kasai and Tsunetoshi Arikado Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan ABSTRACT A Xe flash lamp (FL) heating technique was applied to the post deposition annealing process (PDA) for HfAlOx/SiO2 gate insulator with poly-Si or W/TiN gate electrode in a gate last based process. In the case of W/TiN/HfAlOx/SiO2, CV hysteresis with less than 10mV was achieved using the FL-PDA. However, the FL-PDA increased hysteresis width up to over 100 mV when poly-Si was used as a gate electrode. That occurred also with low temperature (700 °C) rapid thermal PDA process. The lower thermal budget achieved by the flash lamp annealing and the metal gate is effective to suppress the interfacial reaction which causes the traps responsible for the hysteresis. Charge trapping in the W/TiN/HfAlOx/SiO2 was evaluated using CV hysteresis characteristics in the MISFETs and the MIS capacitors. Electron was major trapped charge of the HfAlOx.
INTRODUCTION The combination of high-k gate insulator and metal gate electrode is considered indispensable for MISFETs of 45 nm-technology node and beyond [1]. Hafnium aluminate (HfAlOx) is one of the candidates for high-k dielectric for high performance MISFETs [2]. High temperature processing over 1000 °C, such as post high-k deposition annealing or dopant activation in the gate electrode and the source/drain, is necessary for conventional poly-Si gate MISFET process, which causes interfacial reaction between HfAlOx and underlying SiO2, resulting in large CV hysteresis [2]. The damascene or replacement metal gate process can avoid the high temperature anneal for dopant activation after the high-k insulator formation [3,4]. Also the thermal budget of the PDA should be low because thermally unstable NiSi on the source and drain(S/D) for high performance LSI is formed before the high-k deposition in the metal gate process. The flash lamp annealing process is a strong candidate for very short time heating process compared with conventional RTA process [5,6]. In this work, we applied the flash lamp annealing for PDA process of HfAlOx/SiO2 gate insulator. The electrical properties of flash lamp annealed HfAlOx using n/p-MISFET with W/TiN/HfAlOx/SiO2 gate stack is reported, where these films were formed after source/drain formation and the activation.
EXPERIMENTAL DETAILS Outline of the sample preparation flow is shown in figure 1. The “Gate-Last” MISFET was used for evaluation of electrical properties [7]. Gate insulator and electrode were formed after the
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source/drain formation in a non-self-aligned manner against the source/drain. A 2.5 nm-thick HfAlOx was deposited on a 1nm-thick SiO2 by atomic layer deposition (ALD) at 300 °C. The Hf concentration, Hf/(Hf+Al), was 0.3. Xe lamps were used in the
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