Characteristics of Lateral Capacitor Based on High-K Materials
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0928-GG08-04
Characteristics of Lateral Capacitor Based on High-K Materials Thottam Kalkur1, and Mark Azadpour2 1 University of Colorado at Colorado Springs, Colorado Springs, 80933-7150 2 West Carolina University, Cullowhee, 28723 Abstract: In order to take the advantage of continued interconnect scaling dimensions in very large scale integrated circuit technology, lateral capacitors with BST dielectric have been proposed. The lateral capacitors have been implemented by platinum/titanium metallization patterned by standard photolithographic techniques and ion-milling. The high-K dielectric BST has been deposited by spin-on MOD and radio frequency magnetron sputtering. The capacitance of a lateral capacitor was found to increase with increase in thickness of BST and annealing temperature. The negative temperature dependence capacitance above room temperature shows that BST is in para-electric phase. Introduction: High dielectric constant thin films such as BST and BCTZ are becoming extremely important for the implementation of on-chip decoupling capacitors and varactors [1-5]. Most of the capacitor studies based on high-K dielectrics are confined to parallel plate structures with platinum electrodes. In a parallel plate structure, the characteristics of the capacitor such as dielectric constant, leakage current, breakdown voltage and quality factor depends on the deposition of electrodes and the high-K dielectric. The capacitance density of parallel plate capacitance depends mainly on the thickness of the dielectric. Recently, in integrated circuits, as the line width is extended to deep submicron geometries, lateral capacitors are becoming extremely important to implement high capacitance density. The capacitance C12, between two interconnect lines in an integrated circuit is given by the expression, C12 = εox lint (tint/S)p where εox is the permittivity of the oxide between interconnect, lint is the length of interconnect, tint is the thickness of interconnect metal, S is the spacing between the lines and p is a fitting parameter to account for fringing field effects[6]. Figure 1 shows the variation capacitance per unit area with interconnect spacing for lateral capacitors for p=1 and assuming interconnect width is the same as the spacing. With continued scaling of interconnect dimensions, the capacitance density increases significantly. Therefore, in lateral capacitors, patterning of electrodes plays a dominant role in capacitance characteristics in determining the capacitance density[7,8]. The main advantage in this technology, once the pattering of electrodes are performed, the high capacitance can be achieved by the deposition of high-K dielectric. In this paper we are presenting our preliminary results on the implementation of lateral capacitors using high-dielectric constant thin film BST.
Capcitance in pF/sq.cm
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Interconnect spacing in microns
Figure 1 Variation of capacitance with interconnect spacing for lateral capacitor.
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