A SVPWM Control Strategy for Capacitor Voltage Balancing of Flying Capacitor Based 4-Level NPC Inverter
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ORIGINAL ARTICLE
A SVPWM Control Strategy for Capacitor Voltage Balancing of Flying Capacitor Based 4‑Level NPC Inverter R. Palanisamy1 · V. Shanmugasundaram2 · S. Vidyasagar1 · V. Kalyanasundaram1 · K. Vijayakumar1 Received: 14 March 2020 / Revised: 10 August 2020 / Accepted: 28 August 2020 © The Korean Institute of Electrical Engineers 2020
Abstract A Space Vector Pulse Width Modulation (SVPWM) control strategy is implemented for capacitor voltage balancing of Flying Capacitor (FC) based 4-level Neutral Point Clamped (NPC) inverter. This flying capacitor based 4-level NPC inverter is developed for medium voltage and high power applications. This system includes 6 power switching devices, 2 clamping diodes and 2 flying capacitors per leg. The flying capacitors ensure to operate inverter normally and all the switching devices share the voltage stresses in identical manner. Also it controls the voltage across each capacitor and maintained at V dc/3 times of applied dc voltage. The proposed SVPWM method takes advantage of utilizing redundancy switching states to control and balance the voltage across the capacitor using nearest switching state vector selection method. Moreover, this system provides reduced total harmonic distortion (THD), and minimized voltage stress. The control technique is implemented without using any look-up tables or effective logic tables or trigonometric functions. The simulation and experimental results of this proposed verified are verified using Matlab-simulink and FPGA controller respectively. Keywords Flying capacitor based NPC inverter (FC-NPC) · Space vector pulse width modulation (SVPWM) · Total harmonic distortion (THD) · Capacitor voltage balancing and voltage stress
1 Introduction In recent years multilevel inverter becomes very admired in medium voltage and high power applications and electrical drives due to merits like: reduced voltage stress, minimized THD, lower Common Mode Voltage, lower switching frequency and minimized switching losses [1, 2]. The classical * R. Palanisamy [email protected] V. Shanmugasundaram [email protected] S. Vidyasagar [email protected] V. Kalyanasundaram [email protected] K. Vijayakumar [email protected] 1
Department of EEE, SRM Institute of Science and Technology, Kattankulathur, Kanchipuram, Tamilnadu, India
Departmentt of EEE, Sona College of Technology, Salem, Tamilnadu, India
2
multilevel inverter topologies are Flying capacitor, cascaded H-bridge, Neutral point clamped inverter and modular multilevel inverter [3]. Each topology has its own merits and demerits. Among various topologies, Neutral point clamped inverter has advantages like single dc source shared to all phases, minimized THD and reduced electromagnetic interference issues [4, 5]. Capacitor voltage imbalance is one of the major drawback of the NPC multilevel inverter. Capacitor voltage imbalance rises due to unequal commutation between the switching devices, non-ideal dc link capacitors, non-uniform switching devices and unequal swit
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