Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design
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April 2021, Vol. 64 149401:1–149401:3 https://doi.org/10.1007/s11432-019-2854-9
Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design Jianjian WANG1,2 , Jinshun BI1* , Gang LIU3 , Hua BAI2 , Kai XI1 , Bo LI1 , Sandip MAJUMDAR1,4 , Lanlong JI1 , Ming LIU1 & Zhangang ZHANG5 1 Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; School of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin 300387, China; 3 Beijing Relitech Co., Ltd., Beijing 100015, China; 4 Department of Science and Technology, ICFAI University Tripura, Agartala 799210, India; 5 Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 510610, China 2
Received 5 October 2019/Revised 8 January 2020/Accepted 18 March 2020/Published online 19 November 2020
Citation Wang J J, Bi J S, Liu G, et al. Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design. Sci China Inf Sci, 2021, 64(4): 149401, https://doi.org/10.1007/s11432-019-2854-9
Dear editor, Non-volatile static random access memory (nvSRAM) with a 6-transistor 2-ferroelectric capacitor (6T2C) structure has been proposed, which meets requirements such as high operating speed and non-volatile memory of the spacecraft and has a wide application prospect in the aerospace field [1, 2]. The single event effects (SEEs) in integrated circuits result from the impact of energetic particles on sensitive areas, which may cause the instantaneous interruption of circuit operation, change in logic state, or even permanent damage to semiconductor integrated circuits [3,4]. However, the influence of SEEs on nvSRAM based on the ferroelectric capacitor (FeCap) still remains unknown. In this study, the nvSRAM cell is implemented using a combination of complementary-metal oxide-semiconductor (CMOS) transistors and Hf0.5 Zr0.5 O2 ferroelectric capacitors. A FeCap macro-model suitable for Hafzirconium-based ferroelectric material is used to simulate the Hf0.5 Zr0.5 O2 FeCap. Compared with traditional static random access memory (SRAM), the proposed nvSRAM features three main stages of operation: store, power-off, and recall. An independent double exponential current pulse is used to simulate the single-event transient current. By applying transient current pulses to the specified sensitive node of the 6T2C memory cell, upsets in logic “1” or “0” states are observed under different operating conditions. The techniques to mitigate SEEs on the proposed nvSRAM are then addressed by changing the key parameters of the FeCap model. Experiment setup. An Hf0.5 Zr0.5 O2 FeCap macro-model was proposed for the 6T2C memory cell. The flow chart for building the model is presented in Figure 1(a). The details can be found in previously published studies [5, 6]. The P-V curve obtained from the macro-model simulation is compared with the measured P-V
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