CMP for Copper TSV Applications
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1249-E01-07
CMP for Copper TSV Applications Max Gage, Feng Liu, Kun Xu, You Wang, Yuchun Wang, Sherry Xia, Wen-Chiang Tu, and Lakshmanan Karuppiah Applied Materials, Inc., CMP Division, Silicon Systems Group 974 E. Arques Avenue, Sunnyvale, CA 94085 ABSTRACT Through-silicon via (TSV) 3-D packaging and integration present many new opportunities and challenges for metals CMP applications. For front-side TSV polishing, challenges include the removal of large amounts of copper overburden, dishing control during copper clearing steps, and removal of large amounts of barrier metal and dielectric layers while still maintaining control over topography and defectivity. Additionally, the choice of barrier material can have significant impact on polishing in terms of the mechanical reliability regarding adhesion between the barrier metal and underlying dielectric layers. This paper will address many of these challenges with an emphasis on innovative technologies for superior process and endpoint controls, such as real-time profile control for thick copper films up to 6µm or more in thickness and automatic endpoint controls for barrier removal and dielectric stopping. The paper will also discuss some salient challenges for back-side TSV polishing, including the handling and polishing of bonded wafer pairs and strategies to minimize handling and polishing damage to the potentially fragile thinned device wafer. Additionally, the development of slurries with highly tunable copper-to-dielectric selectivity will be critical for enabling a wide range of final topographies, depending on requirements for subsequent bonding steps. INTRODUCTION There are various potential TSV integration process flows that include CMP steps, such as the via-first (or via-middle) and via-last schemes depicted in Figure 1. Since TSV is a 3D packaging technology, cost and throughput are critical considerations [1]. Therefore, in order for those integration approaches that include CMP to be adopted, the CMP steps must be able to deliver advantages in performance with respect to relative cost. In general, the requirements of copper CMP for TSV are similar to those for conventional copper CMP for BEOL interconnect structures. However, for TSV, the layers of material to be removed are typically much thicker. Accordingly, a main challenge for a TSV CMP application is the development of a highly efficient process that can remove much larger amounts of copper, barrier, and dielectric materials than typical BEOL CMP processes without sacrificing in the areas of cost and throughput. To meet these challenges and requirements, efforts have been focused on developing technologies for superior process control and optimization of consumables that offer the appropriate balance of performance and cost [2]. Additional challenges confronted in TSV applications include wafer handling and mechanical integrity. The very thick layers of dielectric, barrier, and copper materials involved in TSV fabrication can impart significant stresses. In extreme cases, the stress can induce
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