Integration Challenges for CMP of Copper
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Integration
Challenges for CMP of Copper
Rajeev Bajaj, Ajoy Zutshi, Rahul Surana, Mehul Naik, and Tony Pan
Post-CMP Cleaning
Abstract As the minimum feature size of microelectronic devices shrinks down to 130 nm, copper has been successfully adopted into logic applications.1–3 Copper requires damascene processing, which involves etching features into a dielectric substrate, filling the features with metal, and removing any excess metal. Therefore, chemical–mechanical planarization (CMP) is a key process in the final definition of the inlaid copper wires on a circuit. A second advance in the back-end processing of copper is the changing of the dielectric from SiO2 to a low- material, which allows a thicker layer of dielectric to be used. Low- dielectric films have much lower mechanical properties than SiO2; consequently, this poses new challenges in developing integration schemes.1,3–8 Keywords: chemical–mechanical planarization, chemical–mechanical polishing, CMP, copper, electroplating, integration, low- dielectric films.
Introduction As the minimum feature size of microelectronic devices shrinks down to 130 nm, copper has been successfully adopted into logic applications.1–3 Copper requires damascene processing, which involves etching features into a dielectric substrate, filling the features with metal, and removing any excess metal. Therefore, chemical– mechanical planarization (CMP) is a key process in the final definition of the inlaid copper wires on a circuit. A second advance in the back-end processing of copper is the changing of the dielectric from SiO2 to a low- material, which allows a thicker layer of dielectric to be used. Low- dielectric films have much lower mechanical properties than SiO2; consequently, this poses new challenges in developing integration schemes, such as achieving sufficient polishing while using very low down forces, minimizing overplating, and even eliminating the mechanical component of CMP altogether.1,3–8
The CMP Process Chemical–mechanical planarization is a polishing technique that combines mechanical and chemical forces to remove layers of material from a substrate. Each
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New approaches are being developed to minimize or completely eliminate the mechanical component from the CMP process for Cu.1,4,8 One approach is to use an electrochemical process for achieving planarization. A technique known as electropolishing substitutes an electric field for the mechanical-force component in CMP to achieve selectivity in material removal.8 Another approach is to perform chemical planarization or spin-etch planarization,1 wherein the wafer is spun at high speeds and the chemical slurry is dispensed from a nozzle to achieve planarization. Spinetch planarization, to be successful, requires an electroplating process that leaves as little excess (“overburden”) metal as possible over densely patterned areas.
new slurry formulation (the chemical component of CMP) requires the optimization of tool parameters such as down force and pad rotation speed. In copper CMP, the chemi
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