Coherent Chip-Scale Modeling for Copper CMP Pattern Dependence

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Coherent Chip-Scale Modeling for Copper CMP Pattern Dependence Hong Cai1, Tae Park1, Duane Boning1, Hyungjun Kim , Youngsoo Kang2, Sibum Kim2, and Jeong-Gun Lee2 1 Microsystems Technology Laboratories, MIT, Cambridge, MA, USA 2 Hynix Semiconductor Inc., System IC R&D Center, Cheongju, Chungbuk, South Korea 2

ABSTRACT In this research, we present an improved and coherent chip-scale model framework for copper bulk polishing, copper over-polishing, and barrier layer polishing. The integration of contact wear and density-step-height models is more seamlessly implemented and addresses inherent shortcomings of the previous model. In the new model, a local density is used instead of the effective density computed by way of a planarization length, and only a contact wear coefficient is used to characterize the long-range planarization capability, thus avoiding the conflict between the planarization length and the contact wear coefficient in capturing topography variation. In addition, the pressure computed for each 240×240 µm block using contact wear is further redistributed, using a linear height vs. pressure model, among 40×40 µm cells within that block. The same model framework is used for different polishing steps, so that it is possible to directly compare basic process characteristics, such as pad stiffness, of different polishing stages. Results with the new model show a significant improvement of the modeling accuracy to less than 100 Å of root mean square error. Furthermore, the new model framework can be adapted for the modeling of multi-level metallization processes. INTRODUCTION Chemical-Mechanical Polishing or Planarization (CMP) and Electrochemical Deposition (ECD) are the dominant fabrication techniques for state of the art copper metallization in integrated circuits (ICs). Copper CMP provides local and global planarization but suffers from problems of dishing and erosion, which are found to be heavily dependent on underlying layout patterns such as pattern density or pattern pitch. The polishing non-uniformity resulting from dishing and erosion leads to potential yield, reliability and manufacturability problems as well as integration difficulties with other processes such as lithography. The surface topography variation can be aggravated by multilevel interconnect structures prevalent in real chips, where the surface non-planarity of lower level copper metallization can influence the higher level topography. Thus, modeling of pattern dependencies is needed in order to understand the fundamental limitations of interconnect fabrication technologies, to verify yield or performance problem areas on product chips, and to assist in a new process design with enhanced robustness, reliability and manufacturability. Unlike in previous technology generations, the ITRS 2003 roadmap [1] also specifically notes the need for such modeling work for current and future technology nodes, with modeling errors within tens of Å. With shrinking of interconnect dimensions (both vertical and lateral) and improvements in CM