Code Generation for Embedded Processors
Modern electronics is driven by the explosive growth of digital communications and multi-media technology. A basic challenge is to design first-time-right complex digital systems, that meet stringent constraints on performance and power dissipation. In or
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CODE GENERATION FOR EMBEDDED PROCESSORS EDITED
BY
Peter MARWEDEL University of Dortmund Dortmund, Germany
• Gert GOOSSENS IMEC Leuven, Belgium
SPRINGER SCIENCE+BUSINESS MEDIA, L L C
Library of Congress Cataloging-in-Publication Data A C L P . Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4613-5983-8 ISBN 978-1-4615-2323-9 (eBook) DOI 10.1007/978-1-4615-2323-9 Copyright © 2002 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 2002 Softcover reprint of the hardcover 1st edition 2002 A l l rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, L L C . Printed on acid-free paper.
This printing is a digital duplication of the original edition.
CONTENTS
CONTRIBUTORS
7
PREFACE
11
Part I
13
1
CODE GENERATION FOR EMBEDDED PROCESSORS: AN INTRODUCTION Peter Manoedel 1 2
3 4 5 6
2
REQUIREMENTS
New, flexible target technologies Design scenarios for embedded processors Requirements for design tools Related work Target models for retargetable compilation Summary
RETARGETABLE CODE GENERATION: KEY ISSUES FOR SUCCESSFUL INTRODUCTION Paul Vanoostende, Etienne Vanzieleghem, Emmanuel Rousseau, Christian Massy and Fhln~ois Gerard 1 2 3 4 5
Introduction DSP-core architecture Selection of the bigb-Ievellanguage Tool support Conclusions
1
14 14 18 20 24 30 31
32 32 34
39 42
47
2
3
CODE GENERATION FOR EMBEDDED PROCESSORS
CHALLENGES IN CODE GENERATION FOR EMBEDDED PROCESSORS Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Liao, Sharad Malik, Ashok Sudarsanam, Steve Tjiang and Albert ",ang Introduction Retargetable code generation Optimization techniques Compiler organization and experimental infrastructure
50 52 61
5
Summary
64
Part II RETARGETABLE CODE GENERATION SYSTEMS 4
~
1 2 3 4
~
65
FLEXWARE: A FLEXIBLE FIRMWARE DEVELOPMENTE~ONMENTFOR
EMBEDDED SYSTEMS
Pierre G. Paulin, Clifford Liem, 7revor C. May and Shailesh Sutanuala
1 2 3 4
5
Introduction INSULIN : instruction set simulation CODESYN : retargetable code generation Conclusion
67 67 69 75 84
CHESS: RETARGETABLE CODE GENERATION FOR EMBEDDED DSP PROCESSORS Dirk Lanneer, Johan Van Praet, Augusli Kifti, Koen Schools, Werner Geurts, Filip Thoen and Gert Goossens
1 2 3 4 5 6 7 8
Introduction Outline of the CHESS environment Processor modelling using the instruction-set graph A bundling technique for code selection A data routing technique for register allocation Global scheduling Results Conclusions
85 85 87 91 93 95 97 98 100
Contents
6
3
AN ILP-BASED APPROACH TO CODE GENERATION
Tom Wilson, Gary Grewal, Shawn Henshall and Dilip Banerji 1 Introduction 2 Background 3
4 5
7
A linear programming view of code generation Overview of the code generation system Final remarks
RETARGETABLE CODE GENERATION FOR PARALLEL, PIPELINED
