Run-time Adaptation for Reconfigurable Embedded Processors
Run-time Adaptation for Reconfigurable Embedded Processors by: Lars Bauer Jörg Henkel Embedded processors are the heart of embedded systems. Reconfigurable embedded processors comprise an extended instruction set that is implemented using a reconfigurable
- PDF / 10,944,182 Bytes
- 237 Pages / 439.37 x 666.142 pts Page_size
- 3 Downloads / 200 Views
wwwwwwwwwwwwww
Lars Bauer Jörg Henkel ●
Run-time Adaptation for Reconfigurable Embedded Processors
Lars Bauer Karlsruhe Institute of Technology Haid-und-Neu-Str. 7 76131 Karlsruhe Germany [email protected]
Jörg Henkel Karlsruhe Institute of Technology Haid-und-Neu-Str. 7 76131 Karlsruhe Germany
ISBN 978-1-4419-7411-2 e-ISBN 978-1-4419-7412-9 DOI 10.1007/978-1-4419-7412-9 Springer New York Dordrecht Heidelberg London © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Contents
1 Introduction................................................................................................ 1.1 Application-Specific Instruction Set Processors................................. 1.2 Reconfigurable Processors.................................................................. 1.2.1 Summary of Reconfigurable Processors................................. 1.3 Contribution of this Monograph......................................................... 1.4 Monograph Outline.............................................................................
1 2 3 4 5 6
2 Background and Related Work................................................................ 2.1 Extensible Processors.......................................................................... 2.2 Reconfigurable Processors.................................................................. 2.2.1 Granularity of the Reconfigurable Fabric............................... 2.2.2 Using and Partitioning the Reconfigurable Area.................... 2.2.3 Coupling Accelerators and the Processor............................... 2.2.4 Reconfigurable Instruction Set Processors............................. 2.3 Summary of Related Work..................................................................
9 9 11 11 17 21 23 26
3 Modular Special Instructions................................................................... 3.1 Problems of State-of-the-Art Monolithic Special Instructions........... 3.2 Hierarchical Special Instruction Composition.................................... 3.3 Example Special Instructions for the ITU-T H.264 Video Encoder Application.......................................... 3.4 Formal Representation and Combination of Modular Special Instructions.............
Data Loading...
