Low Power Techniques for Embedded FPGA Processors
The low-power techniques are essential part of VLSI design due to continuing increase in clock frequency and complexity of chip. The synchronous circuit operates at highest clock frequency. These circuits drive a large load because it has to reach many se
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Abstract The low-power techniques are essential part of VLSI design due to continuing increase in clock frequency and complexity of chip. The synchronous circuit operates at highest clock frequency. These circuits drive a large load because it has to reach many sequential elements throughout the chip. Thus, clock signals have been a great source of power dissipation because of high frequency and load. Since, clock signals are used for synchronization, they does not carry any information and certainly doesn’t perform any computation. Therefore, disabling the clock signal in inactive portions of the circuit is a useful approach for power dissipation reduction. So, by using clock gating we can save power by reducing unnecessary clock activities inside the gated module. In this chapter, we will review some of the techniques available for clock gating. The chapter also presents Register-Transfer Level(RTL) model in Verilog language. Along with RTL model we have also analyzed the behaviors of clock gating technique using waveform.
J. Kathuria (B) HMR Institute of Technology and Management, New Delhi, India e-mail: [email protected] M. A. Khan Department of Computer Science and Engineering, Sharda University, Gr. Noida, India e-mail: [email protected] A. Abraham Machine Intelligence Research Labs (MIR Labs), Auburn, Washington, USA e-mail: [email protected] A. Darwish Helwan University, Cairo, Egypt e-mail: [email protected]
M. A. Khan et al. (eds.), Embedded and Real Time System Development: A Software Engineering Perspective, Studies in Computational Intelligence 520, DOI: 10.1007/978-3-642-40888-5_11, © Springer-Verlag Berlin Heidelberg 2014
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1 Introduction The Moore’s law states that the density of transistors on an Integrated Circuit (IC) will double approximately every two years. However, there are many challenges. The power density of the IC increases exponentially in every generation of technology. We also know that bipolar and nMOS transistors consume energy even in a stable combinatorial state. However, CMOS transistors consume lower power largely because power is dissipated only when they switch states, and not when the state is steady. The power consumption has been always an important area of research in circuit design. Also, there is a paradigm shift from traditional single core computing to multi-core System-on-Chip (SoC). A SoC consists of computational intellectual property cores, analog components, interface and ICs to implement a system on a single-chip. More than billion transistors are expected to be integrated on a single-chip. Multiple cores can run multiple instructions simultaneously, increasing overall speed for programs amenable to parallel computing. Processors were originally developed with only one core. The traditional multiprocessor techniques are no longer efficient because of issues like congestion in supplying instructions and data to the many processors. The Tilera processors has a switch in each core to route data through an on-chip mesh net
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