Comparison of DEM and BEET Linearization Techniques for Flash Analog-to-Digital Converters
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Comparison of DEM and BEET Linearization Techniques for Flash Analog-to-Digital Converters Christopher D. McGuinness · Eric J. Balster · Frank A. Scarpino
Received: 29 June 2012 / Revised: 17 April 2013 © Springer Science+Business Media New York 2013
Abstract Data converter linearization has been a subject of some interest for most of the past decade. New methods of linearizing analog-to-digital converters (ADCs) continue to be developed. Various linearization methods are available but their comparative strengths and weaknesses are not easily recognizable, making it somewhat difficult to determine which compensator would provide maximum benefit for a specific device. This paper provides a novel performance comparison of two promising real-time linearization methods for flash ADCs: the in-device DEM method, and the peripherally-implemented BEET method using SFDR, SINAD, ENOB, and THD as performance metrics. It is found that BEET is the superior compensator for devices with INL values larger than 0.25 LSB and DNL values larger than 0.25 LSB for optimal SFDR. Results from SINAD, ENOB, and THD metrics indicate that BEET is superior compared to DEM for all devices that have INL > 0.05 LSB. Keywords Analog–digital conversion · Nonlinear distortion · Linear approximation · Error correction · Simulation 1 Introduction Analog-to-digital converter (ADC) designers have the challenge of identifying appropriate methods for compensating device nonlinearities. Depending upon the apC.D. McGuinness () · F.A. Scarpino University of Dayton Research Institute, 300 College Park, Dayton, 45469 OH, USA e-mail: [email protected] F.A. Scarpino e-mail: [email protected] E.J. Balster Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, 45469 OH, USA e-mail: [email protected]
Circuits Syst Signal Process
plication or device specifications, laser trimmed components, gain correction, and offset calibration may not yield sufficient quantization linearity. In such situations, nonlinear compensators may be used to improve the converter’s quality. Internal architecture based compensators may be used to achieve this end, such as dynamic element matching (DEM) [3, 13], stochastic flash ADCs [17], and background calibration [7]. For pre-existing devices that do not have internal compensation, however, these methods are not of particular use. Therefore, external methods such as dithering methods [1], Volterra methods [4, 15], and error table methods [6, 16] are useful for post-fabrication ADC linearization. With such a variety of compensators, each with their own strengths and weaknesses, it is difficult to determine which compensator would be best for a particular device family. This paper addresses this design consideration through a broad comparison study of compensation methods applied to 8-bit full flash ADCs. The study can be easily extended to other converter architectures. One in-device method, DEM [12], and one peripheral method, bit-extended error tables (BEET)
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