A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS
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A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS R. Lindsay1, B. Pawlak2, J. Kittl3, K. Henson1, C. Torregiani4, S. Giangrandi4, R. Surdeanu2, W. Vandervorst1, A. Mayur5, J. Ross6, S. McCoy6, J. Gelpey6, K. Elliott6, X. Pages7, A. Satta1, A. Lauwers1, P.Stolk2, and K. Maex1 1
IMEC, Kapeldreef 75, Leuven B3000, Belgium Philips Research Leuven, 3 affiliate researcher at IMEC from Texas Instruments 4 Univ. of Pavia, Pavia, Italy (Masters Stage at Imec) 5 Applied Materials, Santa Clara, CA 6 Vortek Industries, Ltd., Vancouver, Canada 7 ASM International n.v, 3723 BC Bilthoven, The Netherlands 2
ABSTRACT Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture. In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness (4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity. INTRODUCTION Various alternative approaches to form ultra-shallow junctions for the 45nm CMOS node are being intensively studied. Many of these approaches provide junctions that meet the ITRS 2001 [1] requirements for depth, resistance and abruptness but the focus is now on identifying the approaches that create the least serious problems upon integration. The integration itself depends ultimately on whether bulk Si, strained Si, fully depleted SOI, or FinFET architectures are used. There is now little doubt that conventional spike annealing will not provide junctions suitable for all mentioned 45nm CMOS architectures even with co-implantation species or offset spacers. This is shown later. The most popular alternatives at present are Solid Phase Epitaxial Regrowth
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(SPER), Flash Rapid Thermal Annealing (fRTP) and full- and sub-melt Laser Thermal Annealing (LTA). SPER uses the principle that dopants can activate at lower temperatures (e.g. 600C) in amorphous Si (a-Si) than in crystalline Si (c-Si) [2,3,4]. Abov
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