Copper migration during tungsten via formation
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Copper migration during tungsten via formation Jeff Gambino, Ed Cooney, Will Murphy, Cameron Luce, Steve Mongeon, Ning Lai, Bob Zwonik, Felix Anderson, Laura Schutz, Tom C. Lee, Tom McDevitt IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452 ([email protected]) ABSTRACT A yield problem is observed with tungsten vias formed on copper interconnects. Copper migration can occur during chemical vapor deposition (CVD) of tungsten, if there are defects in the liner inside the via. Copper can react quickly with SiH4 during the early stages of tungsten deposition, when SiH4-reduction of WF6 is used. Under severe conditions, large amounts of copper diffuse out of the underlying metal layer, resulting in copper silicide formation in the via and leaving voids in the copper wire. Copper migration can be minimized by reducing the time that the wafers are exposed to SiH4. INTRODUCTION Copper interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability compared to Al interconnects [1]. One challenge with Cu interconnect technology is with packaging, and in particular with wirebonding [2]. Direct wirebonding onto a Cu bond pad is difficult, because Cu oxides form easily in air. Hence, an Albased terminal wiring layer (Al-Cu) is commonly used in the industry [2-4]. If a fine pitch is required for the terminal wiring layer, then W vias are used to connect the final Al wiring layer to the underlying Cu wiring [4]. Although there have been a few reports on the reliability of W vias landing on Cu interconnects [5,6], there have been no publications on process issues associated with these structures. In this study, we report on a yield problem with W vias formed on top of Cu interconnects. EXPERIMENT Samples were fabricated using a 0.18 µm CMOS process with trench-first, dual damascene Cu in an SiO2 dielectric [7]. The test structures have four levels of metal, with copper interconnects at M1 through M3, a single damascene W via at V3, and a final Al wiring layer at M4 (Fig. 1). Tungsten vias in Al technology typically use sputtered Ti/TiN or Ti/W barrier layers [8,9]. The via is then filled with W using chemical vapor deposition (CVD). The tungsten CVD process basically consists of two steps [9,10]. In the first step, a thin layer (50 nm or less) of CVD W is deposited using SiH4-reduction of WF6. The SiH4-reduction process provides good W nucleation on TiN and minimizes the reaction between WF6 and Ti (which can result in insulating films of TiFx). The rest of the film is deposited using H2-reduction of WF6, which has a higher deposition rate and better conformality than the SiH4-reduction process. The W via process used in this study uses a similar process as that outlined above, except that the barrier layer is sputtered TaN/W, rather than Ti/W, because TaN does not react with Cu [11]. It will be shown that the SiH4-reduction process has an important effect on the via yield and microstructure. Hence,
experiments were run with varying times for th
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