Low Resistance Copper Via Technology
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INTRODUCTION As device-size shrinks, interconnect resistance and current density increase, leading to increase of wiring delay and reliability degradation. Cu multilevel metallization (MLM) is essential to solve the problem and to extend LSI scaling. Via technology is one of the critical issues of Cu MLM, because via contact resistance increases by 2 times with every device generation (70% size reduction) due to the reduction of contacting area. Via resistance is a sum of contact resistance at the contacting interface (Re), barrier resistance (Rb), and plug resistance (Rd). Figure 1 shows the calculated trend of via resistance using the SIA Roadmap 1997[1]. The barrier thickness and the resistivity are assumed as l0nm and 300,u flcm, respectively. The specific contact resistance is assumed as 1 X 10' f"2cm 2 , which is typical for the conventional technology [2-4]. As device-size shrinks, R, becomes more dominant in the total via resistance as shown in Fig. 1. It indicates that Rc reduction is a key issue for obtaining low resistance vias. In order to reduce R,, cleaning of Cu surface at the via bottom is important. Since Cu is easily oxidized and, unlike Al, does not form a self-passivation surface layer, the conventional oxygen plasma process at elevated temperature cannot be used for photoresist removal as in the conventional Al based metallization. A SiN layer was used as a cap layer over Cu to prevent excessive oxidation during the photoresist removal processes. The via holes were formed by etching the SiN layer through to the Cu surface using a CHF 3 plasma. After the etching, the Cu
521 Mat. Res. Soc. Symp. Proc. Vol. 564 © 1999 Materials Research Society
surface is contaminated with species such as C(-CH, -CO, -CFx (x=1,2,3)), F(-CFx, CuF), and O(CuO, Cu20). At the same time, dielectric surfaces are contaminated with species such as C(-CH, -CO, -CFx (x=1,2,3)), F(-CFx, CuF), and O(CuO, Cu 20) from our observation using XPS [5]. The contamination on the Cu surface should be removed to reduce R,. The Cu on the dielectric surface diffuses readily into SiO 2. Three types of cleaning have been investigated. They are wet cleaning using dilute HF (DHF) solution [5], plasma cleaning using hydrogen or oxygen [6], and vapor/heat cleaning using hexafluoroacetylacetone (H(hfac)) vapor [6] or annealing in a vacuum (vacuum anneal) [7], which have been investigated by x-ray photoelectron spectroscopy (XPS) with variable take-off angles, combined with charge shift analysis. The Cu surface at the via bottom, the sidewall dielectrics, and the planar, horizontal surfaces surrounding the vias were separately analyzed by this method. Wet cleaning using dilute oxalic acid (DOA) solution has been investigated by total reflection x-ray fluorescence analysis (TRXRF) [8]. Based on the results, we discussed process design for
optimized via cleaning. We propose an optimized sequence for via-cleaning. Direct-contacted vias (Cu-to-Cu) were fabricated to demonstrate the potential of the optimized cleaning [9]. 7
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