Cu-Compatible Ultra-High Permittivity Dielectrics for Embedded Passive Components
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Cu-Compatible Ultra-High Permittivity Dielectrics for Embedded Passive Components Jon F. Ihlefeld1, Angus I. Kingon1, William Borland2, and Jon-Paul Maria1 1 Institute for Electroceramic Thin Films Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695 2 DuPont Electronic Technologies, Research Triangle Park, NC 27709 ABSTRACT Barium titanate thin films have been prepared by chemical solution deposition on 18 µm thick, industry standard copper foils in the absence of chemical barrier layers. The final embodiment exhibits randomly oriented BaTiO3 grains with diameters between 0.1 and 0.2 µm, and an equiaxed morphology. The average film thickness is 0.6 µm and high resolution cross sectional microscopy shows no indication of interfacial phases. The BaTiO3 films are sintered in a high temperature reductive atmosphere such that copper oxidation is avoided. Subsequent lowertemperature, higher oxygen pressure anneals are used to minimize oxygen point defects. Permittivities greater than 3000 are observed, with loss tangents under 2.5%. The BaTiO3 phase exhibits pronounced ferroelectric switching and coercive field values near 20 kV/cm. Temperature dependent measurements indicate a ferroelectric transition near 100 °C with very diffuse character. Combining the approaches of the multilayer capacitor industry with traditional solution processed thin films has allowed pure barium titanate to be integrated with copper. The high sintering temperature – as compared to typical film processing – provides for large grained films and properties consistent with well-prepared ceramics. Integrating BaTiO3 films on copper foil represents an important step towards high capacitance density embedded passive components. INTRODUCTION Embedded decoupling capacitors within the layers of a printed wiring board (PWB) offer the ability to free surface space, increase device reliability, and reduce electromagnetic interference and inductance losses. Surface space is freed as capacitors and interconnects are moved to within the PWB, offering additional board area for integrated circuits (IC’s) and other devices. Device reliability increases due to fewer soldered connections between chips, capacitors, and interconnects. The ability to locate devices directly above decoupling capacitors shortens interconnect lengths, which in turn decreases the lead inductance and increases the maximum frequency of operation [1,2]. Various groups have deposited chemical solutions of barium titanate on platinized silicon substrates in an effort to develop technologies for DRAM [3-6]. Though low loss, high capacitance density material can be prepared on Pt surfaces, this technology is not appropriate for embedded passives given the high cost of Pt, the inherent rigidity of typical silicon substrates, and the large series resistance associated with thin Pt electrodes. As an alternative approach, several groups have pursued preparation of high permittivity dielectrics on thin metal foils [7-9]. The refractoriness and f
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