Current-Stress-Induced Interface States in p-Si Mos Diodes Detected by a.c. Conductance Measurement
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ABSTRACT Effect of Fowler-Nordheim current stress on (100) p-Si metal/oxide/semiconductor diodes have been studied by means of a.c. conductance measurement. Growth of two distinct peaks are observed in the depletion and the inversion resions corresponding to the generation of two kinds of defects in the upper and lower halves of the bandgap. These defects show different behaviors against the current stress in the energy profiles of the density and the capture cross section. The degradation of the Si/SiO 2 interface is discussed in relation to the defect creation.
INTRODUCTION The progress of down-sizing of metal/oxide/semiconductor (MOS) devices has caused an important issue of degradation and time dependent dielectric breakdown (TDDB) of thin silicon dioxide (SiO 2 ) films. The generation of Si/SiO 2 interface states due to FowlerNordheim (F-N) current stress [1]-[3], avalanche injection [4]-[6] or radiation stress [7] has been extensively investigated. Capacitance-voltage (C-V) measurement has been widely used as a useful method to study interface states [8]-[10]. However, this method has a drawback in which all the defects at Si/Si0 2 interface are inclusively measured , even if they have the same or different capture cross sections in the same energy position. On the other hand , conductance-voltage (G-V) characteristic is more sensitive to the existence of interface states , and moreover , provide a way to estimate capture cross section. Thus, the a.c. conductance method [11] can separate defects with different capture cross sections even at the same energy [3],[12],[13]. In this paper, the generation of interface states due F-N current stress on (100) p-Si MOS diodes is described. In the G-V characteristic, two peaks are observed in the depletion and the inversion regions. From the different behaviors of two kinds of defects corresponding to these two peaks in extracted profiles of interface state density and the capture cross section, the degradation of Si/SiO2 interface will be discussed.
SAMPLES AND MEASUREMENT PROCEDURE The samples used were poly-Si gate MOS diodes. The oxide layer with 185A thickness and 3 x 10- 3 cm 2 area was formed on a 10flcm (100) p-Si substrate by 820'C-thermal wet process. No annealing was performed after the gate poly-Si was deposited. The G-V characteristics were measured in the frequency range of 500-100kHz using an HP 4190A gain/phase analyzer before and after constant F-N current stress (1 x 10-'A/cm 2 , negative gate bias) for various periods using a KEITHLEY 237 current source and voltmeter at room 133 Mat. Res. Soc. Symp. Proc. Vol. 391 ©19 95 Materials Research Society
temperature. The obtained data were analyzed by the standard method on the basis of
continuum level model [3],[11]. RESULTS AND DISCUSSION Figure 1 shows an example of the measured Gm-Va curves before and after the F-N current stress for various periods. Two peaks (Gpip and Gp2p) are observed in the inversion region (-0.4,-0.5V) and in the depletion region (around -0.8V) and both of these peaks grow co
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