Cylindrical Nanowire-TFET with Core-Shell Channel Architecture: Design and Investigation
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ORIGINAL PAPER
Cylindrical Nanowire-TFET with Core-Shell Channel Architecture: Design and Investigation Ashok Kumar Gupta 1 & Ashish Raman 1 & Naveen Kumar 1 Received: 9 September 2019 / Accepted: 13 November 2019 # Springer Nature B.V. 2019
Abstract In this paper, a general gate-all-around (GAA) Tunnel Field Effect Transistor (TFET), TFET with novel extended source and drain structure as core-channel regions have been described. In this work, a comparison of the device performance of the cylindrical nanowire-GAA structure, core-extended source GAA structure and core-extended drain GAA structure is presented. Various device parameters like the non-local band to band tunneling, electron concentration, hole concentration, electric field, potential, the gate-to-gate capacitance and transfer characteristics are analyzed. Other important parameters are linearity parameters, which define the distortions and linearity of the device such as Third-order harmonics distortion (HD3), Third-order current intercept point (IIP3), Third-order intermodulation distortions (IMD3) and Third-order Voltage intercept point (VIP3). The increased gate control is observed in the core-extended source/drain structure. The core-extended based source-drain structure has improved the subthreshold by 5 mV/dec and ON-state current by 2 folds. The proposed design can help in improving the gate-all-around structure in terms of analog and linear characteristics. Keywords Gate all around (GAA) . Core-extended source GAA (CES-GAA) . Core-extended drain GAA (CED-GAA) . Linearity parameter
1 Introduction As per Moore’s law the number of transistors doubles per chip every two years [1]. This results in a continuous reduction in the dimension of the MOSFET device. Since the devices are scale down continuously, it turns into performance limitations like short channel effects (SCE), mobility degradation, Drain induced barrier lowering (DIBL), hot carrier effect, etc. [2]. Thus, power consumption becomes a major issue for further scaling of the device parameters. In the case of MOSFET, scaling the supply voltage can minimize the consumption of power [3]. The drain to source current depends on the effective voltage and it can be increased by scaling the threshold voltage. When scaling the threshold-voltage (Vth), the leakage current is exponentially increased [4]. To avoid this problem various nanoscale devices are * Naveen Kumar [email protected] 1
Dr BR Ambedkar National Institute of Technology, Jalandhar, Punjab, India
under the study, among which Tunnel Field Effect Transistor is more attentive due to the very low IOFF current and low subthreshold slope [5]. Unlike the MOSFET, the current conduction phenomenon of TFET (n-type) is based on the band-to-band tunneling of an electron from valance band of the source to the conduction band of the channel instead of forming an inversion layer due to which it does not suffer from short channel effects [2]. Even though TFET has many merits, it still gives the low ON-state current that is the most research topic
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