Investigation of Cylindrical Channel Gate All Around InGaAs/InP Heterojunction Heterodielectric Tunnel FETs
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ORIGINAL PAPER
Investigation of Cylindrical Channel Gate All Around InGaAs/InP Heterojunction Heterodielectric Tunnel FETs P. Vimala 1
&
T. S. Arun Samuel 2
Received: 30 April 2020 / Accepted: 3 September 2020 # Springer Nature B.V. 2020
Abstract This paper investigated the design and TCAD simulation of heterojunction Tunnel Field Effect Transistor (TFET) with dual gate material. The proposed device structure is designed with narrow bandgap semiconductor material InGaAs (0.74 eV) at source region and wider energy bandgap InP (1.34 eV) at channel and drain regions. The narrow bandgap at source/channel junction improves the tunneling generation rate and the wider bandgap at drain/channel junction reduces the ambipolar behavior. In addition to heterojunction, the dual work function at gate Metal (M1) and Metal (M2) and HfO2/SiO2 stacked dielectric helps to improve the band-gap narrowing as well as reduced leakage current. The proposed device electrical parameters such as Surface potential, energy band diagram, electric field, transconductance and drain current has been analyzed. The simulation results show significant improvement in ON current (10−5A/μm) and reduced OFF current (10−12A/μm) in the proposed device structure. The presented result reveals that the InGaAs/InP heterojunction stacked dielectric TFET is a good candidate for low power applications. Keywords Heterojunction TFET . Stacked dielectric . Dual work function
1 Introduction As the integrated circuit technology coming into nanosize, MOSFET undergoes few performance constraints like short channel effects, high leakage current, subthreshold swing limited to 60 mV/dec and so on. To overcome these shortcomings, Tunnel Field Effect Transistor (TFET) is used as an alternate device structure instead of MOSFET. TFET device offers low leakage current and lesser sub threshold swing [1–3]. Similarly, it has low operating voltage and reduced short channel effects (SCEs) to their greater extent for ultra low power applications [4–6]. Although TFET considered as a suitable device for CMOS technology, it also faces certain limitations like reduced ON current and ambipolar behavior.
* P. Vimala [email protected] T. S. Arun Samuel [email protected] 1
Department of ECE, Dayananda Sagar College of Engineering, Bengaluru, India
2
Department of ECE, National Engineering College, Kovilpatti, India
Several research works has been takes place in order to overcome the limitations of TFETs. Due to the higher carrier mobility and direct band gap, III-V semiconductor material based devices are highly preferred. Heterojunction with graded Si/Ge TFET structure [7] improves the ON current by narrowed and lowered the tunneling barrier at source side and also controls the SCEs and ambipolar leakage current. The abrupt switching speed makes the device as an equivalent to the CMOS technology. Graphene nanoribbon Heterojunction dual material gate TFET [8] acts as a good candidate for low power applications by boosting the ON current with the reduction of tunneling widt
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