Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits 2nd Editi
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and inter
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FRONTIERS IN ELECTRONIC TESTING Consulting Editor Vishwani D. Agrawal Books in the series: Digital Timing Measurements – From Scopes and Probes to Timing and Jitter Maichen, W., Vol. 33 ISBN 0-387-32418-0 Fault-Tolerance Techniques for SRAM-based FPGAs Kastensmidt, F.L., Carro, L. (et al.), Vol. 32 ISBN 0-387-31068-1 Data Mining and Diagnosing IC Fails Huisman, L.M., Vol. 31 ISBN 0-387-24993-1 Fault Diagnosis of Analog Integrated Circuits Kabisatpathy, P., Barua, A. (et al.), Vol. 30 ISBN 0-387-25742-X Introduction to Advanced System-on-Chip Test Design and Optimi... Larsson, E., Vol. 29 ISBN: 1-4020-3207-2 Embedded Processor-Based Self-Test Gizopoulos, D. (et al.), Vol. 28 ISBN: 1-4020-2785-0 Advances in Electronic Testing Gizopoulos, D. (et al.), Vol. 27 ISBN: 0-387-29408-2 Testing Static Random Access Memories Hamdioui, S., Vol. 26 ISBN: 1-4020-7752-1 Verification by Error Modeling Redecka, K. and Zilic, Vol. 25 ISBN: 1-4020-7652-5 Elements of STIL: Principles and Applications of IEEE Std. 1450 Maston, G., Taylor, T. (et al.), Vol. 24 ISBN: 1-4020-7637-1 Fault injection Techniques and Tools for Embedded systems Reliability… Benso, A., Prinetto, P. (Eds.), Vol. 23 ISBN: 1-4020-7589-8 Power-Constrained Testing of VLSI Circuits Nicolici, N., Al-Hashimi, B.M., Vol. 22B ISBN: 1-4020-7235-X High Performance Memory Memory Testing Adams, R. Dean, Vol. 22A ISBN: 1-4020-7255-4 SOC (System-on-a-Chip) Testing for Plug and Play Test Automation Chakrabarty, K. (Ed.), Vol. 21 ISBN: 1-4020-7205-8 Test Resource Partitioning for System-on-a-Chip Chakrabarty, K., Iyengar & Chandra (et al.), Vol. 20 ISBN: 1-4020-7119-1 A Designers’ Guide to Built-in Self-Test Stroud, C., Vol. 19 ISBN: 1-4020-7050-0 Boundary-Scan Interconnect Diagnosis de Sousa, J., Cheung, P.Y.K., Vol. 18 ISBN: 0-7923-7314-6
DEFECT-ORIENTED TESTING FOR NANO-METRIC CMOS VLSI CIRCUITS 2nd Edition by
Manoj Sachdev University of Waterloo Ontario, Canada and
José Pineda de Gyvez Philips Research Laboratories, and Eindhoven University of Technology Eindhoven, The Netherlands
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN-10 0-387-46546-4 (HB) ISBN-13 978-0-387-46546-3 (HB) ISBN-10 0-387-46547-2 (e-book) ISBN-13 978-0-387-46547-0 (e-book)
Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com
Printed on acid-free paper
All Rights Reserved © 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.
Dedication
“To Santosh and Baldev Sachdev; Savitri and Dharm Bir Sawhney” Manoj Sachdev
“To my teachers Jochen Jess and Edgar Sánchez-Sinencio for their invaluable knowledge” José Pineda de Gyvez
Contents
Dedication
v
Preface
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