Degradation of TiSi 2 /n + -Polysilicon Interfaces Due to High Temperature Processing
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DEGRADATION OF TiSi /n+-POLYSILICON INTERFACES DUE TO HIGH TEMPERATURE PROCESSING
K. SHENAI, P. A. PIACENTE, G. A. SMITH, N. LEWIS, M. D. McCONNELL, J. F. NORTON, E. L. HALL, and B. J. BALIGA General Electric Corporate Research and Development, River Road, Schenectady, NY 12309
ABSTRACT Analytical results obtained from detailed Secondary Ion Mass Spectrometry (SIMS), Rutherford Backscattering Spectrometry (RBS), Auger analysis, Scanning Electron Microscopy (SEM), and Transmission Electron Microscopy (TEM) of - 2000A TiSi 2 /n - polysilicon interfaces are reported for thermally annealed silicide samples and silicide samples subjected to further high temperature processing. The LPCVD polysilicon was heavily POCI 3 doped at 900° C and TiSi was formed by rf sputtering 1000A Ti and forming the silicide using ?wo successive thermal anneals at 600° C and 800' C in forming gas resulting in a silicide sheet resistance R of 1.45 0/0. The high temperature process stability of the silicide polysilicon interface was investigated by systematically stressing the polycide at process temperatures in the range of 700° C to II00° C. The silicide was stable for temperatures up to 900° C; however, significant degradation in the silicide sheet resistance, phosphorus, silicon, and titanium redistribution, and agglomeration and film breakage of TiSi2 were observed at higher process temperatures.
INTRODUCTION Conventional high voltage discrete and integrated devices are fabricated using heavily POCI 3 doped polysilicon as the gate material [1-3]. Phosphorus redistribution in polysilicon and its segregation at the SiO /Si interface at process temperatures exceeding 1100' C are the key yield limiting factors in this technology. For example, channel shortening in n-channel MOS gate controlled power devices and threshold voltage nonuniformities across the wafer are some of the deleterious effects of heavily POCI 3 doping the polysilicon to reduce the gate sheet resistance. A low gate sheet resistance is necessary to increase the gate switching efficiency, to improve device switching speed and to enhance device reliability under high surge currents typically observed in power devices and integrated
circuits
(4,5].
Refractory metals and their silicides have low sheet resistances when deposited on polysilicon and also form low resistance ohmic contacts to source and drain diffusions [6,7]. Among all the available silicides on silicon and polysilicon, TiSi offers the lowest sheet resistance and can be easily integrated into exishing device and IC fabrication processes [8]; however, it is becoming evident that the high temperature process stability of TiSi is rather limited [9,10]. As the interlevel dielectric deposition/densification temperatures typically exceed 800 °C in most high voltage devices and integrated circuits [1-3], the silicide must be able to withstand process temperatures at least in the range of 800 - I000° C. The integrity of the silicide - polysilicon interface and its consequences on the electrical characteristics of SiO2
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