Density of States in a-Si:H from SCLC and Its Application in Modeling a Vertical TFT
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Density of States in a-Si:H from SCLC and Its Application in Modeling a Vertical TFT Naser Sedghi and Bill Eccleston Department of Electrical Engineering and Electronics, The University of Liverpool, Brownlow Hill, Liverpool, L69 3GJ, UK ABSTRACT Steady-state space-charge limited current (SCLC) measurements are used to investigate the density of states (DOS) in the mobility gap of hydrogenated amorphous silicon (a-Si:H). The density of states is calculated by different methods based on both continuous DOS and discrete traps assumptions. The density of states found by the SCLC measurements is used to set the trap densities and trap energy levels to model a vertical a-Si:H thin-film transistor (TFT) using the Medici device simulation package. The effect of different sets of traps in the bulk of a-Si:H and variation of the physical dimensions of the device on the characteristics of the vertical TFT is studied. The simulation on the space-charge limited current is performed to verify the validity and accuracy of the SCLC method. INTRODUCTION There has recently been a great interest in fabrication of vertical hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT) [1]. As a-Si:H suffers from low carrier mobility, an alternative to increase the speed of operation is reduction of channel length. The vertical TFT allows submicron performance without the need for critical lithography. Computer modeling provides an understanding about the performance of the device to optimize the TFT prior to fabrication. The density of states (DOS) in the mobility gap of a-Si:H has a crucial role on the TFT characteristics. In the present work, a vertical TFT is modeled using the Medici device simulation program. The DOS obtained from the steady-state space-charge limited current (SCLC) measurements have been used to set the traps in TFT simulation. The effect of different trapping conditions and also variation of physical dimensions on the device characteristics are studied. Steady-state SCLC is a simple and reliable method to find the DOS distribution in the band gap of semiconductors and insulators [2]. The methods are based on the assumption of either continuous DOS or discrete trap levels. Nearly all researchers have claimed that a-Si:H has a continuous DOS. However, there are peaks or maximum points in the DOS distribution that can be treated as discrete trap levels. Approximating to discrete trap levels is especially useful when using simulation packages such as Medici in which a limited number of trap levels can be defined. EXPERIMENTAL DETAILS Films of intrinsic a-Si:H with thickness of 0.2 and 0.3 µm were deposited on top of n-type crystalline silicon wafers with resistivity of 2-3 Ωcm. Aluminium, gold, titanium, and chromium dots were then evaporated (sublimed) as top metal contacts on different samples. Although the contact between top metal and intrinsic a-Si:H film is usually rectifying [3], the n-type crystalline silicon can inject substantial number of electrons into the film when a more negative A26.2.1
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